[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/acpi.c: Create Acpigen procedures

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/26335


Change subject: soc/amd/stoneyridge/acpi.c: Create Acpigen procedures
......................................................................

soc/amd/stoneyridge/acpi.c: Create Acpigen procedures

There are some acpigen functionality that have not been implemented. They
are defined as week within acpigen.c, in order to not break the build.
True versions specific for stoneyridge need to be created.

BUG=b:79546790
TEST=Build grunt, Suresh Guttula will validate.

Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/gpio.c
M src/soc/amd/stoneyridge/include/soc/gpio.h
3 files changed, 105 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26335/1

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 02ee6fa..e5a9f6e 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -32,6 +32,7 @@
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <soc/nvs.h>
+#include <soc/gpio.h>
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
@@ -302,3 +303,100 @@
 		acpigen_pop_len();
 	}
 }
+
+static void acpigen_soc_get_gpio_in_local5(uintptr_t addr)
+{
+	/*
+	 *   Store (\_SB.GPR1 (addr), Local5)
+	 * \_SB.GPR1 is used to read control byte 1 from control register.
+	 * / It is defined in gpio_lib.asl. Bytes in big endian.
+	 */
+	acpigen_write_store();
+	acpigen_emit_namestring("\\_SB.GPR1");
+	acpigen_write_integer(addr);
+	acpigen_emit_byte(LOCAL5_OP);
+}
+
+static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
+{
+	if (gpio_num >= GPIO_TOTAL_PINS) {
+		printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
+					" %d\n", gpio_num, GPIO_TOTAL_PINS);
+		return -1;
+	}
+	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+
+	acpigen_soc_get_gpio_in_local5(addr);
+
+	/* If (And (Local5, mask)) */
+	acpigen_write_if_and(LOCAL5_OP, mask);
+
+	/* Store (One, Local0) */
+	acpigen_write_store_ops(ONE_OP, LOCAL0_OP);
+
+	acpigen_pop_len();	/* If */
+
+	/* Else */
+	acpigen_write_else();
+
+	/* Store (Zero, Local0) */
+	acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);
+
+	acpigen_pop_len();	/* Else */
+
+	return 0;
+}
+
+static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
+{
+	if (gpio_num >= GPIO_TOTAL_PINS) {
+		printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
+					" %d\n", gpio_num, GPIO_TOTAL_PINS);
+		return -1;
+	}
+	uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
+
+	acpigen_soc_get_gpio_in_local5(addr);
+
+	if (val) {
+		/* Or (Local5, GPIO_PIN_OUT, Local5) */
+		acpigen_write_or(LOCAL5_OP, GPIO_PIN_OUT, LOCAL5_OP);
+	} else {
+		/* Not (GPIO_PIN_OUT, Local6) */
+		acpigen_write_not(GPIO_PIN_OUT, LOCAL6_OP);
+
+		/* And (Local5, Local6, Local5) */
+		acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);
+	}
+
+	/*
+	 *   SB.GPW1 (addr, Local5)
+	 * \_SB.GPW1 is used to write control byte in control register
+	 * / byte 1. It is defined in gpio_lib.asl. Bytes in big endian.
+	 */
+	acpigen_emit_namestring("\\_SB.GPW1");
+	acpigen_write_integer(addr);
+	acpigen_emit_byte(LOCAL5_OP);
+
+	return 0;
+}
+
+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN);
+}
+
+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT);
+}
+
+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_set_gpio_val(gpio_num, 1);
+}
+
+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_set_gpio_val(gpio_num, 0);
+}
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index 4520df7..ed040a3 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -20,7 +20,7 @@
 #include <gpio.h>
 #include <soc/gpio.h>
 
-static uintptr_t gpio_get_address(gpio_t gpio_num)
+uintptr_t gpio_get_address(gpio_t gpio_num)
 {
 	uintptr_t gpio_address;
 
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index cbc99e4..120d2ec 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -23,6 +23,10 @@
 #include <soc/iomap.h>
 #include <types.h>
 
+#define GPIO_TOTAL_PINS		24
+#define GPIO_PIN_IN		(1 << 0)	/* for byte access */
+#define GPIO_PIN_OUT		(1 << 6)	/* for byte access */
+
 #define GPIO_EDGE_TRIG		(0 << 8)
 #define GPIO_LEVEL_TRIG		(1 << 8)
 #define GPIO_TRIGGER_MASK	(1 << 8)
@@ -354,6 +358,8 @@
 		.control = GPIO_OUTPUT ## _OUT_ ## direction }
 
 typedef uint32_t gpio_t;
+/* Get the address of the control register of a particular pin */
+uintptr_t gpio_get_address(gpio_t gpio_num);
 
 /* Update interrupt settings for given GPIO */
 void gpio_set_interrupt(gpio_t gpio, uint32_t flags);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68
Gerrit-Change-Number: 26335
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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