<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26335">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge/acpi.c: Create Acpigen procedures<br><br>There are some acpigen functionality that have not been implemented. They<br>are defined as week within acpigen.c, in order to not break the build.<br>True versions specific for stoneyridge need to be created.<br><br>BUG=b:79546790<br>TEST=Build grunt, Suresh Guttula will validate.<br><br>Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/gpio.c<br>M src/soc/amd/stoneyridge/include/soc/gpio.h<br>3 files changed, 105 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26335/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c</span><br><span>index 02ee6fa..e5a9f6e 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi.c</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi.c</span><br><span>@@ -32,6 +32,7 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/southbridge.h></span><br><span> #include <soc/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio.h></span><br><span> </span><br><span> unsigned long acpi_fill_madt(unsigned long current)</span><br><span> {</span><br><span>@@ -302,3 +303,100 @@</span><br><span> acpigen_pop_len();</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void acpigen_soc_get_gpio_in_local5(uintptr_t addr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Store (\_SB.GPR1 (addr), Local5)</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_SB.GPR1 is used to read control byte 1 from control register.</span><br><span style="color: hsl(120, 100%, 40%);">+ * / It is defined in gpio_lib.asl. Bytes in big endian.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_store();</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_emit_namestring("\\_SB.GPR1");</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_integer(addr);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_emit_byte(LOCAL5_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio_num >= GPIO_TOTAL_PINS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"</span><br><span style="color: hsl(120, 100%, 40%);">+ " %d\n", gpio_num, GPIO_TOTAL_PINS);</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_soc_get_gpio_in_local5(addr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* If (And (Local5, mask)) */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_if_and(LOCAL5_OP, mask);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Store (One, Local0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_store_ops(ONE_OP, LOCAL0_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_pop_len(); /* If */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Else */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_else();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Store (Zero, Local0) */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_pop_len(); /* Else */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpio_num >= GPIO_TOTAL_PINS) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"</span><br><span style="color: hsl(120, 100%, 40%);">+ " %d\n", gpio_num, GPIO_TOTAL_PINS);</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_soc_get_gpio_in_local5(addr);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (val) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Or (Local5, GPIO_PIN_OUT, Local5) */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_or(LOCAL5_OP, GPIO_PIN_OUT, LOCAL5_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+ } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Not (GPIO_PIN_OUT, Local6) */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_not(GPIO_PIN_OUT, LOCAL6_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* And (Local5, Local6, Local5) */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SB.GPW1 (addr, Local5)</span><br><span style="color: hsl(120, 100%, 40%);">+ * \_SB.GPW1 is used to write control byte in control register</span><br><span style="color: hsl(120, 100%, 40%);">+ * / byte 1. It is defined in gpio_lib.asl. Bytes in big endian.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_emit_namestring("\\_SB.GPW1");</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_write_integer(addr);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpigen_emit_byte(LOCAL5_OP);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpigen_soc_set_gpio_val(gpio_num, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return acpigen_soc_set_gpio_val(gpio_num, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c</span><br><span>index 4520df7..ed040a3 100644</span><br><span>--- a/src/soc/amd/stoneyridge/gpio.c</span><br><span>+++ b/src/soc/amd/stoneyridge/gpio.c</span><br><span>@@ -20,7 +20,7 @@</span><br><span> #include <gpio.h></span><br><span> #include <soc/gpio.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static uintptr_t gpio_get_address(gpio_t gpio_num)</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t gpio_get_address(gpio_t gpio_num)</span><br><span> {</span><br><span> uintptr_t gpio_address;</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>index cbc99e4..120d2ec 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h</span><br><span>@@ -23,6 +23,10 @@</span><br><span> #include <soc/iomap.h></span><br><span> #include <types.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_TOTAL_PINS 24</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PIN_IN (1 << 0) /* for byte access */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PIN_OUT (1 << 6) /* for byte access */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #define GPIO_EDGE_TRIG (0 << 8)</span><br><span> #define GPIO_LEVEL_TRIG (1 << 8)</span><br><span> #define GPIO_TRIGGER_MASK (1 << 8)</span><br><span>@@ -354,6 +358,8 @@</span><br><span> .control = GPIO_OUTPUT ## _OUT_ ## direction }</span><br><span> </span><br><span> typedef uint32_t gpio_t;</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get the address of the control register of a particular pin */</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t gpio_get_address(gpio_t gpio_num);</span><br><span> </span><br><span> /* Update interrupt settings for given GPIO */</span><br><span> void gpio_set_interrupt(gpio_t gpio, uint32_t flags);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26335">change 26335</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26335"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68 </div>
<div style="display:none"> Gerrit-Change-Number: 26335 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>