[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variants/nocturne: enable I2C #5 bus
Nick Vaccaro (Code Review)
gerrit at coreboot.org
Wed May 16 11:56:04 CEST 2018
Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/26319
Change subject: mb/google/poppy/variants/nocturne: enable I2C #5 bus
......................................................................
mb/google/poppy/variants/nocturne: enable I2C #5 bus
BUG=b:79784124
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' and verify i2c bus #5
is detected.
Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda
Signed-off-by: Nick Vaccaro <nvaccaro at google.com>
---
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/26319/1
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 61df213..5ab7fe7 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -229,7 +229,7 @@
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoPci,
[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
@@ -266,7 +266,7 @@
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 off end # SATA
device pci 19.0 on end # UART #2
- device pci 19.1 off end # I2C #5
+ device pci 19.1 on end # I2C #5
device pci 19.2 on
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic5b754fb97231aeab0278d71f8ced9343c30feda
Gerrit-Change-Number: 26319
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
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