[coreboot-gerrit] Change in coreboot[master]: cpu/intel/model_2065x: Put stage cache in TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/26298


Change subject: cpu/intel/model_2065x: Put stage cache in TSEG
......................................................................

cpu/intel/model_2065x: Put stage cache in TSEG

TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_2065x/Kconfig
M src/cpu/intel/model_2065x/Makefile.inc
M src/cpu/intel/model_2065x/model_2065x.h
A src/cpu/intel/model_2065x/stage_cache.c
4 files changed, 63 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/26298/1

diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index a01618f..f2f440d 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -21,6 +21,7 @@
 	select TSC_SYNC_MFENCE
 	select CPU_INTEL_COMMON
 	select PARALLEL_MP
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 
 config BOOTBLOCK_CPU_INIT
 	string
@@ -30,6 +31,15 @@
 	hex
 	default 0x800000
 
+config SMM_RESERVED_SIZE
+	hex
+	default 0x100000
+
+# Intel Enhanced Debug region must be 4MB
+config IED_REGION_SIZE
+	hex
+	default 0x400000
+
 config XIP_ROM_SIZE
 	hex
 	default 0x20000
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
index 137d1c9..7d3c7b0 100644
--- a/src/cpu/intel/model_2065x/Makefile.inc
+++ b/src/cpu/intel/model_2065x/Makefile.inc
@@ -18,6 +18,9 @@
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
+romstage-y += stage_cache.c
+ramstage-y += stage_cache.c
+
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
 
 cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index d105882..3736dd7 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -92,4 +92,26 @@
 int cpu_config_tdp_levels(void);
 #endif
 
+/*
+ * Region of SMM space is reserved for multipurpose use. It falls below
+ * the IED region and above the SMM handler.
+ */
+#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
+#define RESERVED_SMM_OFFSET \
+	(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
+
+/* Sanity check config options. */
+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
+#endif
+#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
+# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
+#endif
+#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
+# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
+#endif
+#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
+# error "CONFIG_IED_REGION_SIZE is not a power of 2"
+#endif
+
 #endif
diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c
new file mode 100644
index 0000000..be25ba1
--- /dev/null
+++ b/src/cpu/intel/model_2065x/stage_cache.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <stage_cache.h>
+#include "model_2065x.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	/*
+	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+	 * The top of RAM is defined to be the TSEG base address.
+	 */
+	*size = RESERVED_SMM_SIZE;
+	*base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);
+}

-- 
To view, visit https://review.coreboot.org/26298
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Gerrit-Change-Number: 26298
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180515/e12d2140/attachment-0001.html>