<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26298">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/model_2065x: Put stage cache in TSEG<br><br>TSEG is not accessible in ring 0 after it is locked in ramstage, in<br>contrast with cbmem which remains accessible. Assuming SMM does not<br>touch the cache this is a good region to cache stages.<br><br>Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_2065x/Kconfig<br>M src/cpu/intel/model_2065x/Makefile.inc<br>M src/cpu/intel/model_2065x/model_2065x.h<br>A src/cpu/intel/model_2065x/stage_cache.c<br>4 files changed, 63 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/26298/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig</span><br><span>index a01618f..f2f440d 100644</span><br><span>--- a/src/cpu/intel/model_2065x/Kconfig</span><br><span>+++ b/src/cpu/intel/model_2065x/Kconfig</span><br><span>@@ -21,6 +21,7 @@</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select CPU_INTEL_COMMON</span><br><span> select PARALLEL_MP</span><br><span style="color: hsl(120, 100%, 40%);">+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM</span><br><span> </span><br><span> config BOOTBLOCK_CPU_INIT</span><br><span> string</span><br><span>@@ -30,6 +31,15 @@</span><br><span> hex</span><br><span> default 0x800000</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SMM_RESERVED_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x100000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# Intel Enhanced Debug region must be 4MB</span><br><span style="color: hsl(120, 100%, 40%);">+config IED_REGION_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x400000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config XIP_ROM_SIZE</span><br><span> hex</span><br><span> default 0x20000</span><br><span>diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc</span><br><span>index 137d1c9..7d3c7b0 100644</span><br><span>--- a/src/cpu/intel/model_2065x/Makefile.inc</span><br><span>+++ b/src/cpu/intel/model_2065x/Makefile.inc</span><br><span>@@ -18,6 +18,9 @@</span><br><span> </span><br><span> smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += stage_cache.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin</span><br><span> </span><br><span> cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc</span><br><span>diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>index d105882..3736dd7 100644</span><br><span>--- a/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>+++ b/src/cpu/intel/model_2065x/model_2065x.h</span><br><span>@@ -92,4 +92,26 @@</span><br><span> int cpu_config_tdp_levels(void);</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Region of SMM space is reserved for multipurpose use. It falls below</span><br><span style="color: hsl(120, 100%, 40%);">+ * the IED region and above the SMM handler.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define RESERVED_SMM_OFFSET \</span><br><span style="color: hsl(120, 100%, 40%);">+ (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Sanity check config options. */</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONFIG_SMM_TSEG_SIZE < 0x800000)</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_SMM_TSEG_SIZE is not a power of 2"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)</span><br><span style="color: hsl(120, 100%, 40%);">+# error "CONFIG_IED_REGION_SIZE is not a power of 2"</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif</span><br><span>diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c</span><br><span>new file mode 100644</span><br><span>index 0000000..be25ba1</span><br><span>--- /dev/null</span><br><span>+++ b/src/cpu/intel/model_2065x/stage_cache.c</span><br><span>@@ -0,0 +1,28 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2015 Google, Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <stage_cache.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "model_2065x.h"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void stage_cache_external_region(void **base, size_t *size)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.</span><br><span style="color: hsl(120, 100%, 40%);">+ * The top of RAM is defined to be the TSEG base address.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ *size = RESERVED_SMM_SIZE;</span><br><span style="color: hsl(120, 100%, 40%);">+ *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26298">change 26298</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 </div>
<div style="display:none"> Gerrit-Change-Number: 26298 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>