[coreboot-gerrit] Change in coreboot[master]: atlas ish: ish configuration

[Li1 Feng (Code Review)]

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/26277


Change subject: atlas ish: ish configuration
......................................................................

atlas ish: ish configuration

ISH is set as PCI device 0x13. ISH Uart0, I2c0, GPIO Gp1
and Gp2 are configured.

Previous flag "IshEnable" is removed.
Flag "SOC_ISH_ENABLE" is used to enable ISH in coreboot.
In file src/mainboard/google/poppy/Kconfig.name,
find section "config BOARD_GOOGLE_ATLAS", and add "select
SOC_ISH_ENABLE"

BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. Console output of ISH
showed on serial port.

Change-Id: I606705bed4030469b71ef630cfdd974601a4f899
Signed-off-by: li feng <li1.feng at intel.com>
---
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/gpio.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
6 files changed, 20 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/26277/1

diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 8ae9b05..0b2907b 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -45,7 +45,6 @@
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"
 	register "ScsSdCardEnabled" = "0"
-	register "IshEnable" = "0"		# FIXME: enable once ISH is ready
 	register "PttSwitch" = "0"
 	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
@@ -242,6 +241,7 @@
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 13.0 on  end # Integrated Sensor Hub
 		device pci 14.0 on  end # USB xHCI
 		device pci 14.1 on  end # USB xDCI (OTG)
 		device pci 14.2 on  end # Thermal Subsystem
diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c
index c1b3ccc..ef03be2 100644
--- a/src/mainboard/google/poppy/variants/atlas/gpio.c
+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c
@@ -51,10 +51,15 @@
 	PAD_CFG_NC(GPP_A17),
 	/* A18 : ISH_GP0 ==> ISH_GP0 */
 	PAD_CFG_NC(GPP_A18),
+#if (IS_ENABLED(CONFIG_SOC_ISH_ENABLE))
 	/* A19 : ISH_GP1 ==> TRACKPAD_INT_L */
-	PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST),
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
 	/* A20 : ISH_GP2 ==> ISH_UART0_RXD */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+#else
+	PAD_CFG_NC(GPP_A19),
 	PAD_CFG_NC(GPP_A20),
+#endif
 	/* A21 : ISH_GP3 */
 	PAD_CFG_NC(GPP_A21),
 	/* A22 : ISH_GP4 */
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 326b847..f5a0952 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -10,6 +10,10 @@
 	help
 	  Intel Kabylake support
 
+config SOC_ISH_ENABLE
+	bool
+	default n
+
 if SOC_INTEL_SKYLAKE
 
 config CPU_SPECIFIC_OPTIONS
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index bb2ecaa..6cca24a 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -136,7 +136,7 @@
 	params->ScsEmmcEnabled = config->ScsEmmcEnabled;
 	params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
 	params->ScsSdCardEnabled = config->ScsSdCardEnabled;
-	params->IshEnable = 0;
+	params->IshEnable = IS_ENABLED(CONFIG_SOC_ISH_ENABLE);
 	params->EnableAzalia = config->EnableAzalia;
 	params->IoBufferOwnership = config->IoBufferOwnership;
 	params->DspEnable = config->DspEnable;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 2523554..be4237b 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -289,7 +289,7 @@
 	u8 ScsSdCardEnabled;
 
 	/* Integrated Sensor */
-	u8 IshEnable;
+	/* IshEnable is replaced by flag SOC_ISH_ENABLE */
 
 	u8 PttSwitch;
 	u8 HeciTimeouts;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index a4867ea..44fc26e 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -206,7 +206,13 @@
 	params->ScsEmmcEnabled = config->ScsEmmcEnabled;
 	params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
 	params->ScsSdCardEnabled = config->ScsSdCardEnabled;
-	params->PchIshEnable = config->IshEnable;
+	params->PchIshEnable = IS_ENABLED(CONFIG_SOC_ISH_ENABLE);
+	if (params->PchIshEnable) {
+		params->PchIshUart0GpioAssign = 1;
+		params->PchIshI2c0GpioAssign = 1;
+		params->PchIshGp1GpioAssign = 1;
+		params->PchIshGp2GpioAssign = 1;
+	}
 	params->PchHdaEnable = config->EnableAzalia;
 	params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
 	params->PchHdaDspEnable = config->DspEnable;

-- 
To view, visit https://review.coreboot.org/26277
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I606705bed4030469b71ef630cfdd974601a4f899
Gerrit-Change-Number: 26277
Gerrit-PatchSet: 1
Gerrit-Owner: Li1 Feng <li1.feng at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180514/fe495dcc/attachment-0001.html>