<p>Li1 Feng has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26277">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">atlas ish: ish configuration<br><br>ISH is set as PCI device 0x13. ISH Uart0, I2c0, GPIO Gp1<br>and Gp2 are configured.<br><br>Previous flag "IshEnable" is removed.<br>Flag "SOC_ISH_ENABLE" is used to enable ISH in coreboot.<br>In file src/mainboard/google/poppy/Kconfig.name,<br>find section "config BOARD_GOOGLE_ATLAS", and add "select<br>SOC_ISH_ENABLE"<br><br>BUG=b:79244403<br>BRANCH=none<br>TEST=Verified on Atlas board with ISH rework. Console output of ISH<br>showed on serial port.<br><br>Change-Id: I606705bed4030469b71ef630cfdd974601a4f899<br>Signed-off-by: li feng <li1.feng@intel.com><br>---<br>M src/mainboard/google/poppy/variants/atlas/devicetree.cb<br>M src/mainboard/google/poppy/variants/atlas/gpio.c<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>6 files changed, 20 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/26277/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>index 8ae9b05..0b2907b 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb</span><br><span>@@ -45,7 +45,6 @@</span><br><span> register "ScsEmmcEnabled" = "1"</span><br><span> register "ScsEmmcHs400Enabled" = "1"</span><br><span> register "ScsSdCardEnabled" = "0"</span><br><span style="color: hsl(0, 100%, 40%);">- register "IshEnable" = "0" # FIXME: enable once ISH is ready</span><br><span> register "PttSwitch" = "0"</span><br><span> register "InternalGfx" = "1"</span><br><span> register "SkipExtGfxScan" = "1"</span><br><span>@@ -242,6 +241,7 @@</span><br><span> device domain 0 on</span><br><span> device pci 00.0 on end # Host Bridge</span><br><span> device pci 02.0 on end # Integrated Graphics Device</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 13.0 on end # Integrated Sensor Hub</span><br><span> device pci 14.0 on end # USB xHCI</span><br><span> device pci 14.1 on end # USB xDCI (OTG)</span><br><span> device pci 14.2 on end # Thermal Subsystem</span><br><span>diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>index c1b3ccc..ef03be2 100644</span><br><span>--- a/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c</span><br><span>@@ -51,10 +51,15 @@</span><br><span> PAD_CFG_NC(GPP_A17),</span><br><span> /* A18 : ISH_GP0 ==> ISH_GP0 */</span><br><span> PAD_CFG_NC(GPP_A18),</span><br><span style="color: hsl(120, 100%, 40%);">+#if (IS_ENABLED(CONFIG_SOC_ISH_ENABLE))</span><br><span> /* A19 : ISH_GP1 ==> TRACKPAD_INT_L */</span><br><span style="color: hsl(0, 100%, 40%);">- PAD_CFG_GPI_APIC(GPP_A19, NONE, PLTRST),</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),</span><br><span> /* A20 : ISH_GP2 ==> ISH_UART0_RXD */</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ PAD_CFG_NC(GPP_A19),</span><br><span> PAD_CFG_NC(GPP_A20),</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> /* A21 : ISH_GP3 */</span><br><span> PAD_CFG_NC(GPP_A21),</span><br><span> /* A22 : ISH_GP4 */</span><br><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index 326b847..f5a0952 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -10,6 +10,10 @@</span><br><span> help</span><br><span> Intel Kabylake support</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_ISH_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if SOC_INTEL_SKYLAKE</span><br><span> </span><br><span> config CPU_SPECIFIC_OPTIONS</span><br><span>diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c</span><br><span>index bb2ecaa..6cca24a 100644</span><br><span>--- a/src/soc/intel/skylake/chip.c</span><br><span>+++ b/src/soc/intel/skylake/chip.c</span><br><span>@@ -136,7 +136,7 @@</span><br><span> params->ScsEmmcEnabled = config->ScsEmmcEnabled;</span><br><span> params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;</span><br><span> params->ScsSdCardEnabled = config->ScsSdCardEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->IshEnable = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->IshEnable = IS_ENABLED(CONFIG_SOC_ISH_ENABLE);</span><br><span> params->EnableAzalia = config->EnableAzalia;</span><br><span> params->IoBufferOwnership = config->IoBufferOwnership;</span><br><span> params->DspEnable = config->DspEnable;</span><br><span>diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h</span><br><span>index 2523554..be4237b 100644</span><br><span>--- a/src/soc/intel/skylake/chip.h</span><br><span>+++ b/src/soc/intel/skylake/chip.h</span><br><span>@@ -289,7 +289,7 @@</span><br><span> u8 ScsSdCardEnabled;</span><br><span> </span><br><span> /* Integrated Sensor */</span><br><span style="color: hsl(0, 100%, 40%);">- u8 IshEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ /* IshEnable is replaced by flag SOC_ISH_ENABLE */</span><br><span> </span><br><span> u8 PttSwitch;</span><br><span> u8 HeciTimeouts;</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index a4867ea..44fc26e 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -206,7 +206,13 @@</span><br><span> params->ScsEmmcEnabled = config->ScsEmmcEnabled;</span><br><span> params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;</span><br><span> params->ScsSdCardEnabled = config->ScsSdCardEnabled;</span><br><span style="color: hsl(0, 100%, 40%);">- params->PchIshEnable = config->IshEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchIshEnable = IS_ENABLED(CONFIG_SOC_ISH_ENABLE);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (params->PchIshEnable) {</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchIshUart0GpioAssign = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchIshI2c0GpioAssign = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchIshGp1GpioAssign = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ params->PchIshGp2GpioAssign = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> params->PchHdaEnable = config->EnableAzalia;</span><br><span> params->PchHdaIoBufferOwnership = config->IoBufferOwnership;</span><br><span> params->PchHdaDspEnable = config->DspEnable;</span><br><span></span><br></pre><p>To view, visit <a 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I606705bed4030469b71ef630cfdd974601a4f899 </div>
<div style="display:none"> Gerrit-Change-Number: 26277 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Li1 Feng <li1.feng@intel.com> </div>