[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun May 13 13:48:38 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26260
Change subject: sb/intel/lynxpoint: Get rid of device_t
......................................................................
sb/intel/lynxpoint: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I51df9873b4111d28a911a2ac1d14b9600a3ef5dd
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.c
M src/southbridge/intel/lynxpoint/pch.h
M src/southbridge/intel/lynxpoint/pci.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/pmutil.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/smihandler.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/intel/lynxpoint/watchdog.c
15 files changed, 72 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/26260/1
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index 0b1acdd..6b4e4ef 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -154,7 +154,7 @@
}
}
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d1d00c6..a2a6198 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -109,9 +109,9 @@
* 0x80 - The PIRQ is not routed.
*/
-static void pch_pirq_init(device_t dev)
+static void pch_pirq_init(struct device *dev)
{
- device_t irq_dev;
+ struct device *irq_dev;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -151,7 +151,7 @@
}
}
-static void pch_gpi_routing(device_t dev)
+static void pch_gpi_routing(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -180,7 +180,7 @@
pci_write_config32(dev, GPIO_ROUT, reg32);
}
-static void pch_power_options(device_t dev)
+static void pch_power_options(struct device *dev)
{
u8 reg8;
u16 reg16;
@@ -420,7 +420,7 @@
reg32 = RCBA32(HPTC);
}
-static void enable_clock_gating(device_t dev)
+static void enable_clock_gating(struct device *dev)
{
/* LynxPoint Mobile */
u32 reg32;
@@ -445,7 +445,7 @@
RCBA32_OR(0x38c0, 0x7); // SPI Dynamic
}
-static void enable_lp_clock_gating(device_t dev)
+static void enable_lp_clock_gating(struct device *dev)
{
/* LynxPoint LP */
u32 reg32;
@@ -595,7 +595,7 @@
pch_fixups(dev);
}
-static void pch_lpc_add_mmio_resources(device_t dev)
+static void pch_lpc_add_mmio_resources(struct device *dev)
{
u32 reg;
struct resource *res;
@@ -657,7 +657,7 @@
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)
+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)
{
struct resource *res;
@@ -670,7 +670,7 @@
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)
+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)
{
/*
* Check if the register is enabled. If so and the base exceeds the
@@ -683,7 +683,7 @@
}
}
-static void pch_lpc_add_io_resources(device_t dev)
+static void pch_lpc_add_io_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@@ -708,7 +708,7 @@
pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
}
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
{
global_nvs_t *gnvs;
@@ -727,7 +727,7 @@
memset(gnvs, 0, sizeof(global_nvs_t));
}
-static void pch_lpc_enable(device_t dev)
+static void pch_lpc_enable(struct device *dev)
{
/* Enable PCH Display Port */
RCBA16(DISPBDF) = 0x0010;
@@ -736,7 +736,7 @@
pch_enable(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -747,7 +747,7 @@
}
}
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs;
@@ -788,7 +788,7 @@
}
}
-static unsigned long southbridge_write_acpi_tables(device_t device,
+static unsigned long southbridge_write_acpi_tables(struct device *device,
unsigned long start,
struct acpi_rsdp *rsdp)
{
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 6168498..00e6bde 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -52,12 +52,12 @@
[ME_DISABLE_BIOS_PATH] = "Disable",
[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
};
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
#endif
/* MMIO base address for MEI interface */
static u32 *mei_base_address;
-void intel_me_mbp_clear(device_t dev);
+void intel_me_mbp_clear(struct device *dev);
#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -112,7 +112,7 @@
mei_dump(ptr, dword, offset, "WRITE");
}
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -413,7 +413,7 @@
* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
* state machine on the BIOS end doesn't match the ME's state machine.
*/
-static void intel_me_mbp_give_up(device_t dev)
+static void intel_me_mbp_give_up(struct device *dev)
{
struct mei_csr csr;
@@ -429,7 +429,7 @@
* mbp clear routine. This will wait for the ME to indicate that
* the MBP has been read and cleared.
*/
-void intel_me_mbp_clear(device_t dev)
+void intel_me_mbp_clear(struct device *dev)
{
int count;
struct me_hfs2 hfs2;
@@ -658,7 +658,7 @@
}
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -728,7 +728,7 @@
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -758,7 +758,7 @@
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -805,7 +805,7 @@
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
me_bios_path path = intel_me_path(dev);
@@ -858,7 +858,7 @@
*/
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -873,7 +873,7 @@
.set_subsystem = set_subsystem,
};
-static void intel_me_enable(device_t dev)
+static void intel_me_enable(struct device *dev)
{
/* Avoid talking to the device in S3 path */
if (acpi_is_wakeup_s3()) {
@@ -940,7 +940,7 @@
* mbp seems to be following its own flow, let's retrieve it in a dedicated
* function.
*/
-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
{
mbp_header mbp_hdr;
u32 me2host_pending;
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 1a390cc..eb1ffb8 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -23,7 +23,7 @@
#include <device/pci_def.h>
#include "pch.h"
-static device_t pch_get_lpc_device(void)
+static struct device *pch_get_lpc_device(void)
{
#ifdef __SMM__
return PCI_DEV(0, 0x1f, 0);
@@ -80,7 +80,7 @@
#ifndef __SMM__
/* Put device in D3Hot Power State */
-static void pch_enable_d3hot(device_t dev)
+static void pch_enable_d3hot(struct device *dev)
{
u32 reg32 = pci_read_config32(dev, PCH_PCS);
reg32 |= PCH_PCS_PS_D3HOT;
@@ -88,7 +88,7 @@
}
/* Set bit in Function Disble register to hide this device */
-void pch_disable_devfn(device_t dev)
+void pch_disable_devfn(struct device *dev)
{
switch (dev->path.pci.devfn) {
case PCI_DEVFN(19, 0): /* Audio DSP */
@@ -285,7 +285,7 @@
pch_iobp_write(address, data);
}
-void pch_enable(device_t dev)
+void pch_enable(struct device *dev)
{
u32 reg32;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index f14a339..6be1121 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -93,9 +93,9 @@
#if defined (__SMM__) && !defined(__ASSEMBLER__)
void intel_pch_finalize_smm(void);
-void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ);
-void usb_ehci_disable(device_t dev);
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
+void usb_ehci_sleep_prepare(struct device *dev, u8 slp_typ);
+void usb_ehci_disable(struct device *dev);
+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ);
void usb_xhci_route_all(void);
#endif
@@ -179,8 +179,8 @@
#include <device/device.h>
#include <arch/acpi.h>
#include "chip.h"
-void pch_enable(device_t dev);
-void pch_disable_devfn(device_t dev);
+void pch_enable(struct device *dev);
+void pch_disable_devfn(struct device *dev);
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c
index e2e052b..3c43210 100644
--- a/src/southbridge/intel/lynxpoint/pci.c
+++ b/src/southbridge/intel/lynxpoint/pci.c
@@ -104,7 +104,7 @@
ich_pci_dev_enable_resources(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 73c81b4..590a7e2 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -42,7 +42,7 @@
int coalesce;
int gbe_port;
int num_ports;
- device_t ports[MAX_NUM_ROOT_PORTS];
+ struct device *ports[MAX_NUM_ROOT_PORTS];
};
static struct root_port_config rpc;
@@ -55,18 +55,18 @@
return H_NUM_ROOT_PORTS;
}
-static inline int root_port_is_first(device_t dev)
+static inline int root_port_is_first(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == 0;
}
-static inline int root_port_is_last(device_t dev)
+static inline int root_port_is_last(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
}
/* Root ports are numbered 1..N in the documentation. */
-static inline int root_port_number(device_t dev)
+static inline int root_port_number(struct device *dev)
{
return PCI_FUNC(dev->path.pci.devfn) + 1;
}
@@ -101,7 +101,7 @@
}
}
-static void root_port_init_config(device_t dev)
+static void root_port_init_config(struct device *dev)
{
int rp;
@@ -154,7 +154,7 @@
/* Update devicetree with new Root Port function number assignment */
static void pch_pcie_device_set_func(int index, int pci_func)
{
- device_t dev;
+ struct device *dev;
unsigned new_devfn;
dev = rpc.ports[index];
@@ -187,7 +187,7 @@
enabled_ports = 0;
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
int rp;
dev = rpc.ports[i];
@@ -275,7 +275,7 @@
pcie_enable_clock_gating();
for (i = 0; i < rpc.num_ports; i++) {
- device_t dev;
+ struct device *dev;
u32 reg32;
dev = rpc.ports[i];
@@ -328,7 +328,7 @@
RCBA32(RPFN) = rpc.new_rpfn;
}
-static void root_port_mark_disable(device_t dev)
+static void root_port_mark_disable(struct device *dev)
{
/* Mark device as disabled. */
dev->enabled = 0;
@@ -336,7 +336,7 @@
rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
}
-static void root_port_check_disable(device_t dev)
+static void root_port_check_disable(struct device *dev)
{
int rp;
int is_lp;
@@ -695,7 +695,7 @@
pci_write_config16(dev, 0x1e, reg16);
}
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
/* Add this device to the root port config structure. */
root_port_init_config(dev);
@@ -715,7 +715,7 @@
root_port_commit_config();
}
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 00a6e65..a8a94c3 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -558,9 +558,9 @@
int rtc_failure(void)
{
#if defined(__SIMPLE_DEVICE__)
- device_t dev = PCI_DEV(0, 31, 0);
+ struct device *dev = PCI_DEV(0, 31, 0);
#else
- device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0));
#endif
return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);
}
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index c45579b..9cec15e 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -301,7 +301,7 @@
pci_write_config32(dev, 0x300, reg32);
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -322,7 +322,7 @@
pci_write_config16(dev, 0x90, map);
}
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 7d6608f..85b23e4 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -237,7 +237,7 @@
}
}
-static void serialio_set_subsystem(device_t dev, unsigned vendor,
+static void serialio_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c
index ccb5ea0..97cdb8e 100644
--- a/src/southbridge/intel/lynxpoint/smbus.c
+++ b/src/southbridge/intel/lynxpoint/smbus.c
@@ -25,7 +25,7 @@
#include <southbridge/intel/common/smbus.h>
#include "pch.h"
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
@@ -41,7 +41,7 @@
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -54,7 +54,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
{
u16 device;
struct resource *res;
@@ -71,7 +71,7 @@
.write_byte = lsmbus_write_byte,
};
-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -86,7 +86,7 @@
.set_subsystem = smbus_set_subsystem,
};
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index dcec3f0..ed04094 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -75,7 +75,7 @@
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
+ struct device *dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index e2486cf..491128c 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -25,7 +25,7 @@
#ifdef __SMM__
-void usb_ehci_disable(device_t dev)
+void usb_ehci_disable(struct device *dev)
{
u16 reg16;
u32 reg32;
@@ -57,7 +57,7 @@
}
/* Handler for EHCI controller on entry to S3/S4/S5 */
-void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)
+void usb_ehci_sleep_prepare(struct device *dev, u8 slp_typ)
{
u32 reg32;
u8 *bar0_base;
@@ -164,7 +164,7 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 28e6521..3134060 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -24,7 +24,7 @@
typedef struct southbridge_intel_lynxpoint_config config_t;
-static u8 *usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(struct device *dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -35,7 +35,7 @@
return (u8 *)(mem_base & ~0xf);
}
-static int usb_xhci_port_count_usb3(device_t dev)
+static int usb_xhci_port_count_usb3(struct device *dev)
{
if (pch_is_lp()) {
/* LynxPoint-LP has 4 SS ports */
@@ -83,7 +83,7 @@
* b) Poll for warm reset complete
* c) Write 1 to port change status bits
*/
-static void usb_xhci_reset_usb3(device_t dev, int all)
+static void usb_xhci_reset_usb3(struct device *dev, int all)
{
u32 status, port_disabled;
int timeout, port;
@@ -156,7 +156,7 @@
#ifdef __SMM__
/* Handler for XHCI controller on entry to S3/S4/S5 */
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
@@ -240,7 +240,7 @@
#else /* !__SMM__ */
-static void usb_xhci_clock_gating(device_t dev)
+static void usb_xhci_clock_gating(struct device *dev)
{
u32 reg32;
u16 reg16;
@@ -287,7 +287,7 @@
pci_write_config32(dev, 0xa4, reg32);
}
-static void usb_xhci_init(device_t dev)
+static void usb_xhci_init(struct device *dev)
{
u32 reg32;
u16 reg16;
@@ -361,7 +361,7 @@
}
}
-static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,
+static void usb_xhci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
if (!vendor || !device) {
diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c
index 74f69b0..9a867e4 100644
--- a/src/southbridge/intel/lynxpoint/watchdog.c
+++ b/src/southbridge/intel/lynxpoint/watchdog.c
@@ -28,7 +28,7 @@
//
void watchdog_off(void)
{
- device_t dev;
+ struct device *dev;
unsigned long value, base;
/* Turn off the ICH7 watchdog. */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I51df9873b4111d28a911a2ac1d14b9600a3ef5dd
Gerrit-Change-Number: 26260
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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