<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26260">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/lynxpoint: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I51df9873b4111d28a911a2ac1d14b9600a3ef5dd<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/lynxpoint/azalia.c<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/me_9.x.c<br>M src/southbridge/intel/lynxpoint/pch.c<br>M src/southbridge/intel/lynxpoint/pch.h<br>M src/southbridge/intel/lynxpoint/pci.c<br>M src/southbridge/intel/lynxpoint/pcie.c<br>M src/southbridge/intel/lynxpoint/pmutil.c<br>M src/southbridge/intel/lynxpoint/sata.c<br>M src/southbridge/intel/lynxpoint/serialio.c<br>M src/southbridge/intel/lynxpoint/smbus.c<br>M src/southbridge/intel/lynxpoint/smihandler.c<br>M src/southbridge/intel/lynxpoint/usb_ehci.c<br>M src/southbridge/intel/lynxpoint/usb_xhci.c<br>M src/southbridge/intel/lynxpoint/watchdog.c<br>15 files changed, 72 insertions(+), 72 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/26260/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c</span><br><span>index 0b1acdd..6b4e4ef 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/azalia.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/azalia.c</span><br><span>@@ -154,7 +154,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>      if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>index d1d00c6..a2a6198 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/lpc.c</span><br><span>@@ -109,9 +109,9 @@</span><br><span>  * 0x80 - The PIRQ is not routed.</span><br><span>  */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pirq_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *irq_dev;</span><br><span>      /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span> </span><br><span>@@ -151,7 +151,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_gpi_routing(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_gpi_routing(struct device *dev)</span><br><span> {</span><br><span>    /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -180,7 +180,7 @@</span><br><span>  pci_write_config32(dev, GPIO_ROUT, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_power_options(struct device *dev)</span><br><span> {</span><br><span>       u8 reg8;</span><br><span>     u16 reg16;</span><br><span>@@ -420,7 +420,7 @@</span><br><span>     reg32 = RCBA32(HPTC);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_clock_gating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_clock_gating(struct device *dev)</span><br><span> {</span><br><span>        /* LynxPoint Mobile */</span><br><span>       u32 reg32;</span><br><span>@@ -445,7 +445,7 @@</span><br><span>     RCBA32_OR(0x38c0, 0x7); // SPI Dynamic</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_lp_clock_gating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_lp_clock_gating(struct device *dev)</span><br><span> {</span><br><span>         /* LynxPoint LP */</span><br><span>   u32 reg32;</span><br><span>@@ -595,7 +595,7 @@</span><br><span>     pch_fixups(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_mmio_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_mmio_resources(struct device *dev)</span><br><span> {</span><br><span>       u32 reg;</span><br><span>     struct resource *res;</span><br><span>@@ -657,7 +657,7 @@</span><br><span>  * Note: this function assumes there is no overlap with the default LPC device's</span><br><span>  * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index)</span><br><span> {</span><br><span>    struct resource *res;</span><br><span> </span><br><span>@@ -670,7 +670,7 @@</span><br><span>      res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index)</span><br><span> {</span><br><span>        /*</span><br><span>    * Check if the register is enabled. If so and the base exceeds the</span><br><span>@@ -683,7 +683,7 @@</span><br><span>    }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_add_io_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_add_io_resources(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res;</span><br><span>        config_t *config = dev->chip_info;</span><br><span>@@ -708,7 +708,7 @@</span><br><span>  pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span>  global_nvs_t *gnvs;</span><br><span> </span><br><span>@@ -727,7 +727,7 @@</span><br><span>                memset(gnvs, 0, sizeof(global_nvs_t));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable(struct device *dev)</span><br><span> {</span><br><span>         /* Enable PCH Display Port */</span><br><span>        RCBA16(DISPBDF) = 0x0010;</span><br><span>@@ -736,7 +736,7 @@</span><br><span>      pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>     if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -747,7 +747,7 @@</span><br><span>       }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_inject_dsdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_inject_dsdt(struct device *dev)</span><br><span> {</span><br><span>    global_nvs_t *gnvs;</span><br><span> </span><br><span>@@ -788,7 +788,7 @@</span><br><span>        }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static unsigned long southbridge_write_acpi_tables(device_t device,</span><br><span style="color: hsl(120, 100%, 40%);">+static unsigned long southbridge_write_acpi_tables(struct device *device,</span><br><span>                                                unsigned long start,</span><br><span>                                                 struct acpi_rsdp *rsdp)</span><br><span> {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>index 6168498..00e6bde 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>@@ -52,12 +52,12 @@</span><br><span>   [ME_DISABLE_BIOS_PATH]          = "Disable",</span><br><span>       [ME_FIRMWARE_UPDATE_BIOS_PATH]  = "Firmware Update",</span><br><span> };</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);</span><br><span> #endif</span><br><span> </span><br><span> /* MMIO base address for MEI interface */</span><br><span> static u32 *mei_base_address;</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_me_mbp_clear(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_me_mbp_clear(struct device *dev);</span><br><span> </span><br><span> #if IS_ENABLED(CONFIG_DEBUG_INTEL_ME)</span><br><span> static void mei_dump(void *ptr, int dword, int offset, const char *type)</span><br><span>@@ -112,7 +112,7 @@</span><br><span>      mei_dump(ptr, dword, offset, "WRITE");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span> {</span><br><span>   u32 dword = pci_read_config32(dev, offset);</span><br><span>  memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -413,7 +413,7 @@</span><br><span>  * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read</span><br><span>  * state machine on the BIOS end doesn't match the ME's state machine.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_mbp_give_up(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_mbp_give_up(struct device *dev)</span><br><span> {</span><br><span>        struct mei_csr csr;</span><br><span> </span><br><span>@@ -429,7 +429,7 @@</span><br><span>  * mbp clear routine. This will wait for the ME to indicate that</span><br><span>  * the MBP has been read and cleared.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-void intel_me_mbp_clear(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void intel_me_mbp_clear(struct device *dev)</span><br><span> {</span><br><span>     int count;</span><br><span>   struct me_hfs2 hfs2;</span><br><span>@@ -658,7 +658,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span> {</span><br><span>    me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span>    struct me_hfs hfs;</span><br><span>@@ -728,7 +728,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res;</span><br><span>        struct mei_csr host;</span><br><span>@@ -758,7 +758,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span> {</span><br><span>   struct me_heres status;</span><br><span>      u32 extend[8] = {0};</span><br><span>@@ -805,7 +805,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span> {</span><br><span>        struct southbridge_intel_lynxpoint_config *config = dev->chip_info;</span><br><span>       me_bios_path path = intel_me_path(dev);</span><br><span>@@ -858,7 +858,7 @@</span><br><span>         */</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>  if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -873,7 +873,7 @@</span><br><span>       .set_subsystem = set_subsystem,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_enable(struct device *dev)</span><br><span> {</span><br><span>     /* Avoid talking to the device in S3 path */</span><br><span>         if (acpi_is_wakeup_s3()) {</span><br><span>@@ -940,7 +940,7 @@</span><br><span>  * mbp seems to be following its own flow, let's retrieve it in a dedicated</span><br><span>  * function.</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)</span><br><span> {</span><br><span>    mbp_header mbp_hdr;</span><br><span>  u32 me2host_pending;</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c</span><br><span>index 1a390cc..eb1ffb8 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.c</span><br><span>@@ -23,7 +23,7 @@</span><br><span> #include <device/pci_def.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static device_t pch_get_lpc_device(void)</span><br><span style="color: hsl(120, 100%, 40%);">+static struct device *pch_get_lpc_device(void)</span><br><span> {</span><br><span> #ifdef __SMM__</span><br><span>      return PCI_DEV(0, 0x1f, 0);</span><br><span>@@ -80,7 +80,7 @@</span><br><span> #ifndef __SMM__</span><br><span> </span><br><span> /* Put device in D3Hot Power State */</span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_enable_d3hot(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_enable_d3hot(struct device *dev)</span><br><span> {</span><br><span>     u32 reg32 = pci_read_config32(dev, PCH_PCS);</span><br><span>         reg32 |= PCH_PCS_PS_D3HOT;</span><br><span>@@ -88,7 +88,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Set bit in Function Disble register to hide this device */</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_disable_devfn(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_disable_devfn(struct device *dev)</span><br><span> {</span><br><span>        switch (dev->path.pci.devfn) {</span><br><span>    case PCI_DEVFN(19, 0): /* Audio DSP */</span><br><span>@@ -285,7 +285,7 @@</span><br><span>         pch_iobp_write(address, data);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(struct device *dev)</span><br><span> {</span><br><span>       u32 reg32;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>index f14a339..6be1121 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pch.h</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pch.h</span><br><span>@@ -93,9 +93,9 @@</span><br><span> </span><br><span> #if defined (__SMM__) && !defined(__ASSEMBLER__)</span><br><span> void intel_pch_finalize_smm(void);</span><br><span style="color: hsl(0, 100%, 40%);">-void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ);</span><br><span style="color: hsl(0, 100%, 40%);">-void usb_ehci_disable(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_ehci_sleep_prepare(struct device *dev, u8 slp_typ);</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_ehci_disable(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ);</span><br><span> void usb_xhci_route_all(void);</span><br><span> #endif</span><br><span> </span><br><span>@@ -179,8 +179,8 @@</span><br><span> #include <device/device.h></span><br><span> #include <arch/acpi.h></span><br><span> #include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev);</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_disable_devfn(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(struct device *dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_disable_devfn(struct device *dev);</span><br><span> u32 pch_iobp_read(u32 address);</span><br><span> void pch_iobp_write(u32 address, u32 data);</span><br><span> void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c</span><br><span>index e2e052b..3c43210 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pci.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pci.c</span><br><span>@@ -104,7 +104,7 @@</span><br><span>   ich_pci_dev_enable_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   /* NOTE: This is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>index 73c81b4..590a7e2 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pcie.c</span><br><span>@@ -42,7 +42,7 @@</span><br><span>   int coalesce;</span><br><span>        int gbe_port;</span><br><span>        int num_ports;</span><br><span style="color: hsl(0, 100%, 40%);">-  device_t ports[MAX_NUM_ROOT_PORTS];</span><br><span style="color: hsl(120, 100%, 40%);">+   struct device *ports[MAX_NUM_ROOT_PORTS];</span><br><span> };</span><br><span> </span><br><span> static struct root_port_config rpc;</span><br><span>@@ -55,18 +55,18 @@</span><br><span>             return H_NUM_ROOT_PORTS;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_is_first(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_is_first(struct device *dev)</span><br><span> {</span><br><span>   return PCI_FUNC(dev->path.pci.devfn) == 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_is_last(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_is_last(struct device *dev)</span><br><span> {</span><br><span>        return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);</span><br><span> }</span><br><span> </span><br><span> /* Root ports are numbered 1..N in the documentation. */</span><br><span style="color: hsl(0, 100%, 40%);">-static inline int root_port_number(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline int root_port_number(struct device *dev)</span><br><span> {</span><br><span>    return PCI_FUNC(dev->path.pci.devfn) + 1;</span><br><span> }</span><br><span>@@ -101,7 +101,7 @@</span><br><span>      }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_init_config(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_init_config(struct device *dev)</span><br><span> {</span><br><span>        int rp;</span><br><span> </span><br><span>@@ -154,7 +154,7 @@</span><br><span> /* Update devicetree with new Root Port function number assignment */</span><br><span> static void pch_pcie_device_set_func(int index, int pci_func)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  unsigned new_devfn;</span><br><span> </span><br><span>      dev = rpc.ports[index];</span><br><span>@@ -187,7 +187,7 @@</span><br><span>        enabled_ports = 0;</span><br><span> </span><br><span>       for (i = 0; i < rpc.num_ports; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+         struct device *dev;</span><br><span>          int rp;</span><br><span> </span><br><span>          dev = rpc.ports[i];</span><br><span>@@ -275,7 +275,7 @@</span><br><span>    pcie_enable_clock_gating();</span><br><span> </span><br><span>      for (i = 0; i < rpc.num_ports; i++) {</span><br><span style="color: hsl(0, 100%, 40%);">-                device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+         struct device *dev;</span><br><span>          u32 reg32;</span><br><span> </span><br><span>               dev = rpc.ports[i];</span><br><span>@@ -328,7 +328,7 @@</span><br><span>    RCBA32(RPFN) = rpc.new_rpfn;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_mark_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_mark_disable(struct device *dev)</span><br><span> {</span><br><span>   /* Mark device as disabled. */</span><br><span>       dev->enabled = 0;</span><br><span>@@ -336,7 +336,7 @@</span><br><span>   rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void root_port_check_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void root_port_check_disable(struct device *dev)</span><br><span> {</span><br><span>         int rp;</span><br><span>      int is_lp;</span><br><span>@@ -695,7 +695,7 @@</span><br><span>     pci_write_config16(dev, 0x1e, reg16);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pcie_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pcie_enable(struct device *dev)</span><br><span> {</span><br><span>        /* Add this device to the root port config structure. */</span><br><span>     root_port_init_config(dev);</span><br><span>@@ -715,7 +715,7 @@</span><br><span>            root_port_commit_config();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>         /* NOTE: This is not the default position! */</span><br><span>        if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c</span><br><span>index 00a6e65..a8a94c3 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/pmutil.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/pmutil.c</span><br><span>@@ -558,9 +558,9 @@</span><br><span> int rtc_failure(void)</span><br><span> {</span><br><span> #if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(0, 100%, 40%);">-    device_t dev = PCI_DEV(0, 31, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+     struct device *dev = PCI_DEV(0, 31, 0);</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">-        device_t dev = dev_find_slot(0, PCI_DEVFN(31, 0));</span><br><span style="color: hsl(120, 100%, 40%);">+    struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0));</span><br><span> #endif</span><br><span>   return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD);</span><br><span> }</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c</span><br><span>index c45579b..9cec15e 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/sata.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/sata.c</span><br><span>@@ -301,7 +301,7 @@</span><br><span>        pci_write_config32(dev, 0x300, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span>       /* Get the chip configuration */</span><br><span>     config_t *config = dev->chip_info;</span><br><span>@@ -322,7 +322,7 @@</span><br><span>  pci_write_config16(dev, 0x90, map);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>        if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c</span><br><span>index 7d6608f..85b23e4 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/serialio.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/serialio.c</span><br><span>@@ -237,7 +237,7 @@</span><br><span>  }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void serialio_set_subsystem(device_t dev, unsigned vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void serialio_set_subsystem(struct device *dev, unsigned vendor,</span><br><span>                                    unsigned device)</span><br><span> {</span><br><span>     if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c</span><br><span>index ccb5ea0..97cdb8e 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/smbus.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/smbus.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_smbus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_smbus_init(struct device *dev)</span><br><span> {</span><br><span>   struct resource *res;</span><br><span>        u16 reg16;</span><br><span>@@ -41,7 +41,7 @@</span><br><span>               outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span>         u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -54,7 +54,7 @@</span><br><span>    return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 data)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)</span><br><span> {</span><br><span>        u16 device;</span><br><span>  struct resource *res;</span><br><span>@@ -71,7 +71,7 @@</span><br><span>    .write_byte     = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>    if (!vendor || !device) {</span><br><span>            pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -86,7 +86,7 @@</span><br><span>         .set_subsystem    = smbus_set_subsystem,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_read_resources(struct device *dev)</span><br><span> {</span><br><span>  struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span>        res->base = SMBUS_IO_BASE;</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>index dcec3f0..ed04094 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/smihandler.c</span><br><span>@@ -75,7 +75,7 @@</span><br><span>       for (slot = 0; slot < 0x20; slot++) {</span><br><span>             for (func = 0; func < 8; func++) {</span><br><span>                        u32 reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-                      device_t dev = PCI_DEV(bus, slot, func);</span><br><span style="color: hsl(120, 100%, 40%);">+                      struct device *dev = PCI_DEV(bus, slot, func);</span><br><span> </span><br><span>                   val = pci_read_config32(dev, PCI_VENDOR_ID);</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c</span><br><span>index e2486cf..491128c 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/usb_ehci.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> </span><br><span> #ifdef __SMM__</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void usb_ehci_disable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_ehci_disable(struct device *dev)</span><br><span> {</span><br><span>       u16 reg16;</span><br><span>   u32 reg32;</span><br><span>@@ -57,7 +57,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Handler for EHCI controller on entry to S3/S4/S5 */</span><br><span style="color: hsl(0, 100%, 40%);">-void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_ehci_sleep_prepare(struct device *dev, u8 slp_typ)</span><br><span> {</span><br><span>     u32 reg32;</span><br><span>   u8 *bar0_base;</span><br><span>@@ -164,7 +164,7 @@</span><br><span>         printk(BIOS_DEBUG, "done.\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span>   u8 access_cntl;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c</span><br><span>index 28e6521..3134060 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/usb_xhci.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> </span><br><span> typedef struct southbridge_intel_lynxpoint_config config_t;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u8 *usb_xhci_mem_base(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static u8 *usb_xhci_mem_base(struct device *dev)</span><br><span> {</span><br><span>         u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);</span><br><span> </span><br><span>@@ -35,7 +35,7 @@</span><br><span>   return (u8 *)(mem_base & ~0xf);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int usb_xhci_port_count_usb3(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int usb_xhci_port_count_usb3(struct device *dev)</span><br><span> {</span><br><span>  if (pch_is_lp()) {</span><br><span>           /* LynxPoint-LP has 4 SS ports */</span><br><span>@@ -83,7 +83,7 @@</span><br><span>  *  b) Poll for warm reset complete</span><br><span>  *  c) Write 1 to port change status bits</span><br><span>  */</span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_xhci_reset_usb3(device_t dev, int all)</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_xhci_reset_usb3(struct device *dev, int all)</span><br><span> {</span><br><span>    u32 status, port_disabled;</span><br><span>   int timeout, port;</span><br><span>@@ -156,7 +156,7 @@</span><br><span> #ifdef __SMM__</span><br><span> </span><br><span> /* Handler for XHCI controller on entry to S3/S4/S5 */</span><br><span style="color: hsl(0, 100%, 40%);">-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ)</span><br><span> {</span><br><span>      u16 reg16;</span><br><span>   u32 reg32;</span><br><span>@@ -240,7 +240,7 @@</span><br><span> </span><br><span> #else /* !__SMM__ */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_xhci_clock_gating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_xhci_clock_gating(struct device *dev)</span><br><span> {</span><br><span>  u32 reg32;</span><br><span>   u16 reg16;</span><br><span>@@ -287,7 +287,7 @@</span><br><span>     pci_write_config32(dev, 0xa4, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_xhci_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_xhci_init(struct device *dev)</span><br><span> {</span><br><span>    u32 reg32;</span><br><span>   u16 reg16;</span><br><span>@@ -361,7 +361,7 @@</span><br><span>     }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_xhci_set_subsystem(struct device *dev, unsigned vendor,</span><br><span>                                    unsigned device)</span><br><span> {</span><br><span>     if (!vendor || !device) {</span><br><span>diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c</span><br><span>index 74f69b0..9a867e4 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/watchdog.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/watchdog.c</span><br><span>@@ -28,7 +28,7 @@</span><br><span>   //</span><br><span> void watchdog_off(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">-      device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span>  unsigned long value, base;</span><br><span> </span><br><span>       /* Turn off the ICH7 watchdog. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26260">change 26260</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26260"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I51df9873b4111d28a911a2ac1d14b9600a3ef5dd </div>
<div style="display:none"> Gerrit-Change-Number: 26260 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>