[coreboot-gerrit] Change in coreboot[master]: sb/intel/ibexpeak: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun May 13 13:41:13 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26259
Change subject: sb/intel/ibexpeak: Get rid of device_t
......................................................................
sb/intel/ibexpeak: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I7d9d0a205f9a650eb87bc8f90f2a28a5c4b2891c
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/pch.h
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
8 files changed, 32 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26259/1
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 964c3b2..21692ee 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -314,7 +314,7 @@
pci_write_config8(dev, 0x43, reg8);
}
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index bd12944..7959c39 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -100,9 +100,9 @@
* 0x80 - The PIRQ is not routed.
*/
-static void pch_pirq_init(device_t dev)
+static void pch_pirq_init(struct device *dev)
{
- device_t irq_dev;
+ struct device *irq_dev;
/* Interrupt 11 is not used by legacy devices and so can always be used for
PCI interrupts. Full legacy IRQ routing is complicated and hard to
get right. Fortunately all modern OS use MSI and so it's not that big of
@@ -137,7 +137,7 @@
}
}
-static void pch_gpi_routing(device_t dev)
+static void pch_gpi_routing(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -166,7 +166,7 @@
pci_write_config32(dev, GPIO_ROUT, reg32);
}
-static void pch_power_options(device_t dev)
+static void pch_power_options(struct device *dev)
{
u8 reg8;
u16 reg16, pmbase;
@@ -394,7 +394,7 @@
write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);
}
-static void enable_clock_gating(device_t dev)
+static void enable_clock_gating(struct device *dev)
{
u32 reg32;
u16 reg16;
@@ -532,7 +532,7 @@
pch_fixups(dev);
}
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@@ -593,13 +593,13 @@
}
}
-static void pch_lpc_enable_resources(device_t dev)
+static void pch_lpc_enable_resources(struct device *dev)
{
pch_decode_init(dev);
return pci_dev_enable_resources(dev);
}
-static void pch_lpc_enable(device_t dev)
+static void pch_lpc_enable(struct device *dev)
{
/* Enable PCH Display Port */
RCBA16(DISPBDF) = 0x0010;
@@ -608,7 +608,7 @@
pch_enable(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -619,7 +619,7 @@
}
}
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@@ -647,7 +647,7 @@
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
int c2_latency;
@@ -781,9 +781,9 @@
return "LPCB";
}
-static void southbridge_fill_ssdt(device_t device)
+static void southbridge_fill_ssdt(struct device *device)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index e260650..14fce59 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -115,7 +115,7 @@
}
#ifndef __SMM__
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -425,7 +425,7 @@
#else /* !__SMM__ */
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -492,7 +492,7 @@
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -522,7 +522,7 @@
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -569,14 +569,14 @@
}
/* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
+static void intel_me_hide(struct device *dev)
{
dev->enabled = 0;
pch_enable(dev);
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
me_bios_path path = intel_me_path(dev);
@@ -611,7 +611,7 @@
}
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index d3c5a66..f9583e0 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -57,7 +57,7 @@
#if !defined(__PRE_RAM__)
#if !defined(__SIMPLE_DEVICE__)
#include "chip.h"
-void pch_enable(device_t dev);
+void pch_enable(struct device *dev);
#endif
int pch_silicon_revision(void);
int pch_silicon_type(void);
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 19ef098..960f1bf 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -209,7 +209,7 @@
pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -234,7 +234,7 @@
pci_write_config16(dev, 0x90, map);
}
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -246,7 +246,7 @@
}
}
-static void sata_fill_ssdt(device_t dev)
+static void sata_fill_ssdt(struct device *dev)
{
config_t *config = dev->chip_info;
generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index aea52de..7cf2b38 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -25,7 +25,7 @@
#include <southbridge/intel/common/smbus.h>
#include "pch.h"
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
@@ -41,7 +41,7 @@
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -54,7 +54,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u16 device;
struct resource *res;
@@ -72,7 +72,7 @@
.write_byte = lsmbus_write_byte,
};
-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -87,7 +87,7 @@
.set_subsystem = smbus_set_subsystem,
};
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index 78b5b14..baafa63 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -44,7 +44,7 @@
printk(BIOS_DEBUG, "Thermal init done.\n");
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 315367d..51a6203 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -68,7 +68,7 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
unsigned device)
{
u8 access_cntl;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7d9d0a205f9a650eb87bc8f90f2a28a5c4b2891c
Gerrit-Change-Number: 26259
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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