<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26259">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/ibexpeak: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: I7d9d0a205f9a650eb87bc8f90f2a28a5c4b2891c<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/ibexpeak/azalia.c<br>M src/southbridge/intel/ibexpeak/lpc.c<br>M src/southbridge/intel/ibexpeak/me.c<br>M src/southbridge/intel/ibexpeak/pch.h<br>M src/southbridge/intel/ibexpeak/sata.c<br>M src/southbridge/intel/ibexpeak/smbus.c<br>M src/southbridge/intel/ibexpeak/thermal.c<br>M src/southbridge/intel/ibexpeak/usb_ehci.c<br>8 files changed, 32 insertions(+), 32 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26259/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c</span><br><span>index 964c3b2..21692ee 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/azalia.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/azalia.c</span><br><span>@@ -314,7 +314,7 @@</span><br><span> pci_write_config8(dev, 0x43, reg8);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>index bd12944..7959c39 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/lpc.c</span><br><span>@@ -100,9 +100,9 @@</span><br><span> * 0x80 - The PIRQ is not routed.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_pirq_init(struct device *dev)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *irq_dev;</span><br><span> /* Interrupt 11 is not used by legacy devices and so can always be used for</span><br><span> PCI interrupts. Full legacy IRQ routing is complicated and hard to</span><br><span> get right. Fortunately all modern OS use MSI and so it's not that big of</span><br><span>@@ -137,7 +137,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_gpi_routing(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_gpi_routing(struct device *dev)</span><br><span> {</span><br><span> /* Get the chip configuration */</span><br><span> config_t *config = dev->chip_info;</span><br><span>@@ -166,7 +166,7 @@</span><br><span> pci_write_config32(dev, GPIO_ROUT, reg32);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_power_options(struct device *dev)</span><br><span> {</span><br><span> u8 reg8;</span><br><span> u16 reg16, pmbase;</span><br><span>@@ -394,7 +394,7 @@</span><br><span> write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void enable_clock_gating(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void enable_clock_gating(struct device *dev)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> u16 reg16;</span><br><span>@@ -532,7 +532,7 @@</span><br><span> pch_fixups(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> config_t *config = dev->chip_info;</span><br><span>@@ -593,13 +593,13 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span> pch_decode_init(dev);</span><br><span> return pci_dev_enable_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_lpc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_lpc_enable(struct device *dev)</span><br><span> {</span><br><span> /* Enable PCH Display Port */</span><br><span> RCBA16(DISPBDF) = 0x0010;</span><br><span>@@ -608,7 +608,7 @@</span><br><span> pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -619,7 +619,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_inject_dsdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_inject_dsdt(struct device *dev)</span><br><span> {</span><br><span> global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));</span><br><span> </span><br><span>@@ -647,7 +647,7 @@</span><br><span> </span><br><span> void acpi_fill_fadt(acpi_fadt_t *fadt)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> config_t *chip = dev->chip_info;</span><br><span> u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;</span><br><span> int c2_latency;</span><br><span>@@ -781,9 +781,9 @@</span><br><span> return "LPCB";</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_fill_ssdt(device_t device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_fill_ssdt(struct device *device)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));</span><br><span> config_t *chip = dev->chip_info;</span><br><span> </span><br><span> intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c</span><br><span>index e260650..14fce59 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/me.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/me.c</span><br><span>@@ -115,7 +115,7 @@</span><br><span> }</span><br><span> </span><br><span> #ifndef __SMM__</span><br><span style="color: hsl(0, 100%, 40%);">-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)</span><br><span style="color: hsl(120, 100%, 40%);">+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)</span><br><span> {</span><br><span> u32 dword = pci_read_config32(dev, offset);</span><br><span> memcpy(ptr, &dword, sizeof(dword));</span><br><span>@@ -425,7 +425,7 @@</span><br><span> #else /* !__SMM__ */</span><br><span> </span><br><span> /* Determine the path that we should take based on ME status */</span><br><span style="color: hsl(0, 100%, 40%);">-static me_bios_path intel_me_path(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static me_bios_path intel_me_path(struct device *dev)</span><br><span> {</span><br><span> me_bios_path path = ME_DISABLE_BIOS_PATH;</span><br><span> struct me_hfs hfs;</span><br><span>@@ -492,7 +492,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Prepare ME for MEI messages */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_mei_setup(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_mei_setup(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> struct mei_csr host;</span><br><span>@@ -522,7 +522,7 @@</span><br><span> }</span><br><span> </span><br><span> /* Read the Extend register hash of ME firmware */</span><br><span style="color: hsl(0, 100%, 40%);">-static int intel_me_extend_valid(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static int intel_me_extend_valid(struct device *dev)</span><br><span> {</span><br><span> struct me_heres status;</span><br><span> u32 extend[8] = {0};</span><br><span>@@ -569,14 +569,14 @@</span><br><span> }</span><br><span> </span><br><span> /* Hide the ME virtual PCI devices */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_hide(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_hide(struct device *dev)</span><br><span> {</span><br><span> dev->enabled = 0;</span><br><span> pch_enable(dev);</span><br><span> }</span><br><span> </span><br><span> /* Check whether ME is present and do basic init */</span><br><span style="color: hsl(0, 100%, 40%);">-static void intel_me_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void intel_me_init(struct device *dev)</span><br><span> {</span><br><span> me_bios_path path = intel_me_path(dev);</span><br><span> </span><br><span>@@ -611,7 +611,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>index d3c5a66..f9583e0 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/pch.h</span><br><span>+++ b/src/southbridge/intel/ibexpeak/pch.h</span><br><span>@@ -57,7 +57,7 @@</span><br><span> #if !defined(__PRE_RAM__)</span><br><span> #if !defined(__SIMPLE_DEVICE__)</span><br><span> #include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-void pch_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable(struct device *dev);</span><br><span> #endif</span><br><span> int pch_silicon_revision(void);</span><br><span> int pch_silicon_type(void);</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c</span><br><span>index 19ef098..960f1bf 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/sata.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/sata.c</span><br><span>@@ -209,7 +209,7 @@</span><br><span> pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span> /* Get the chip configuration */</span><br><span> config_t *config = dev->chip_info;</span><br><span>@@ -234,7 +234,7 @@</span><br><span> pci_write_config16(dev, 0x90, map);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -246,7 +246,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_fill_ssdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_fill_ssdt(struct device *dev)</span><br><span> {</span><br><span> config_t *config = dev->chip_info;</span><br><span> generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c</span><br><span>index aea52de..7cf2b38 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/smbus.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/smbus.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "pch.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_smbus_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void pch_smbus_init(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> u16 reg16;</span><br><span>@@ -41,7 +41,7 @@</span><br><span> outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span> u16 device;</span><br><span> struct resource *res;</span><br><span>@@ -54,7 +54,7 @@</span><br><span> return do_smbus_read_byte(res->base, device, address);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)</span><br><span> {</span><br><span> u16 device;</span><br><span> struct resource *res;</span><br><span>@@ -72,7 +72,7 @@</span><br><span> .write_byte = lsmbus_write_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -87,7 +87,7 @@</span><br><span> .set_subsystem = smbus_set_subsystem,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);</span><br><span> res->base = SMBUS_IO_BASE;</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c</span><br><span>index 78b5b14..baafa63 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/thermal.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/thermal.c</span><br><span>@@ -44,7 +44,7 @@</span><br><span> printk(BIOS_DEBUG, "Thermal init done.\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c</span><br><span>index 315367d..51a6203 100644</span><br><span>--- a/src/southbridge/intel/ibexpeak/usb_ehci.c</span><br><span>+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c</span><br><span>@@ -68,7 +68,7 @@</span><br><span> printk(BIOS_DEBUG, "done.\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,</span><br><span style="color: hsl(120, 100%, 40%);">+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,</span><br><span> unsigned device)</span><br><span> {</span><br><span> u8 access_cntl;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26259">change 26259</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26259"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7d9d0a205f9a650eb87bc8f90f2a28a5c4b2891c </div>
<div style="display:none"> Gerrit-Change-Number: 26259 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>