[coreboot-gerrit] Change in coreboot[master]: intel/fsp_rangeley: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun May 13 13:23:42 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26250
Change subject: intel/fsp_rangeley: Get rid of device_t
......................................................................
intel/fsp_rangeley: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/sata.c
M src/southbridge/intel/fsp_rangeley/smbus.c
M src/southbridge/intel/fsp_rangeley/soc.c
M src/southbridge/intel/fsp_rangeley/soc.h
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/fsp_rangeley/watchdog.c
7 files changed, 18 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/26250/1
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index b9af406..a8b8757 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -114,8 +114,8 @@
*/
static void write_pci_config_irqs(void)
{
- device_t irq_dev;
- device_t targ_dev;
+ struct device *irq_dev;
+ struct device *targ_dev;
uint8_t int_line = 0;
uint8_t original_int_pin = 0;
uint8_t new_int_pin = 0;
@@ -198,7 +198,7 @@
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
-static void soc_pirq_init(device_t dev)
+static void soc_pirq_init(struct device *dev)
{
int i, j;
int pirq;
@@ -243,7 +243,7 @@
write_pci_config_irqs();
}
-static void soc_power_options(device_t dev)
+static void soc_power_options(struct device *dev)
{
u8 reg8;
u16 pmbase;
@@ -345,7 +345,7 @@
soc_disable_smm_only_flashing(dev);
}
-static void soc_lpc_read_resources(device_t dev)
+static void soc_lpc_read_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@@ -406,17 +406,17 @@
}
}
-static void soc_lpc_enable_resources(device_t dev)
+static void soc_lpc_enable_resources(struct device *dev)
{
return pci_dev_enable_resources(dev);
}
-static void soc_lpc_enable(device_t dev)
+static void soc_lpc_enable(struct device *dev)
{
soc_enable(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -427,7 +427,7 @@
}
}
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index 624af23..c1d5749 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -91,11 +91,11 @@
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
}
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c
index 9ea8126..a91e659 100644
--- a/src/southbridge/intel/fsp_rangeley/smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/smbus.c
@@ -25,7 +25,7 @@
#include <southbridge/intel/common/smbus.h>
#include "soc.h"
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -42,7 +42,7 @@
.read_byte = lsmbus_read_byte,
};
-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -57,7 +57,7 @@
.set_subsystem = smbus_set_subsystem,
};
-static void rangeley_smbus_read_resources(device_t dev)
+static void rangeley_smbus_read_resources(struct device *dev)
{
struct resource *res;
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index df4edc0f..13b64c4 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -66,7 +66,7 @@
-void soc_enable(device_t dev)
+void soc_enable(struct device *dev)
{
u32 reg32;
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 764bf97..eaf9556 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -60,7 +60,7 @@
int soc_silicon_revision(void);
int soc_silicon_type(void);
int soc_silicon_supported(int type, int rev);
-void soc_enable(device_t dev);
+void soc_enable(struct device *dev);
#include <arch/acpi.h>
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index 933a966..0512bcf 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -343,7 +343,7 @@
{
int ich_version = 0;
uint8_t bios_cntl;
- device_t dev;
+ struct device *dev;
uint32_t ids;
uint16_t vendor_id, device_id;
diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c
index 4b109fd..ff1c571 100644
--- a/src/southbridge/intel/fsp_rangeley/watchdog.c
+++ b/src/southbridge/intel/fsp_rangeley/watchdog.c
@@ -25,7 +25,7 @@
void watchdog_off(void)
{
- device_t dev;
+ struct device *dev;
u32 value, abase;
/* Turn off the watchdog. */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554
Gerrit-Change-Number: 26250
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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