<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26250">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp_rangeley: Get rid of device_t<br><br>Use of device_t has been abandoned in ramstage.<br><br>Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/intel/fsp_rangeley/lpc.c<br>M src/southbridge/intel/fsp_rangeley/sata.c<br>M src/southbridge/intel/fsp_rangeley/smbus.c<br>M src/southbridge/intel/fsp_rangeley/soc.c<br>M src/southbridge/intel/fsp_rangeley/soc.h<br>M src/southbridge/intel/fsp_rangeley/spi.c<br>M src/southbridge/intel/fsp_rangeley/watchdog.c<br>7 files changed, 18 insertions(+), 18 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/26250/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c</span><br><span>index b9af406..a8b8757 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/lpc.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/lpc.c</span><br><span>@@ -114,8 +114,8 @@</span><br><span> */</span><br><span> static void write_pci_config_irqs(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t irq_dev;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t targ_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *irq_dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *targ_dev;</span><br><span> uint8_t int_line = 0;</span><br><span> uint8_t original_int_pin = 0;</span><br><span> uint8_t new_int_pin = 0;</span><br><span>@@ -198,7 +198,7 @@</span><br><span> printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_pirq_init(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_pirq_init(struct device *dev)</span><br><span> {</span><br><span> int i, j;</span><br><span> int pirq;</span><br><span>@@ -243,7 +243,7 @@</span><br><span> write_pci_config_irqs();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_power_options(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_power_options(struct device *dev)</span><br><span> {</span><br><span> u8 reg8;</span><br><span> u16 pmbase;</span><br><span>@@ -345,7 +345,7 @@</span><br><span> soc_disable_smm_only_flashing(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_lpc_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_lpc_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> config_t *config = dev->chip_info;</span><br><span>@@ -406,17 +406,17 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_lpc_enable_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_lpc_enable_resources(struct device *dev)</span><br><span> {</span><br><span> return pci_dev_enable_resources(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_lpc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void soc_lpc_enable(struct device *dev)</span><br><span> {</span><br><span> soc_enable(dev);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -427,7 +427,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void southbridge_inject_dsdt(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void southbridge_inject_dsdt(struct device *dev)</span><br><span> {</span><br><span> global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c</span><br><span>index 624af23..c1d5749 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/sata.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/sata.c</span><br><span>@@ -91,11 +91,11 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_enable(struct device *dev)</span><br><span> {</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c</span><br><span>index 9ea8126..a91e659 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/smbus.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/smbus.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> #include <southbridge/intel/common/smbus.h></span><br><span> #include "soc.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static int lsmbus_read_byte(device_t dev, u8 address)</span><br><span style="color: hsl(120, 100%, 40%);">+static int lsmbus_read_byte(struct device *dev, u8 address)</span><br><span> {</span><br><span> u16 device;</span><br><span> struct resource *res;</span><br><span>@@ -42,7 +42,7 @@</span><br><span> .read_byte = lsmbus_read_byte,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)</span><br><span style="color: hsl(120, 100%, 40%);">+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)</span><br><span> {</span><br><span> if (!vendor || !device) {</span><br><span> pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,</span><br><span>@@ -57,7 +57,7 @@</span><br><span> .set_subsystem = smbus_set_subsystem,</span><br><span> };</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void rangeley_smbus_read_resources(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+static void rangeley_smbus_read_resources(struct device *dev)</span><br><span> {</span><br><span> struct resource *res;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c</span><br><span>index df4edc0f..13b64c4 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/soc.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/soc.c</span><br><span>@@ -66,7 +66,7 @@</span><br><span> </span><br><span> </span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void soc_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_enable(struct device *dev)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>index 764bf97..eaf9556 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/soc.h</span><br><span>@@ -60,7 +60,7 @@</span><br><span> int soc_silicon_revision(void);</span><br><span> int soc_silicon_type(void);</span><br><span> int soc_silicon_supported(int type, int rev);</span><br><span style="color: hsl(0, 100%, 40%);">-void soc_enable(device_t dev);</span><br><span style="color: hsl(120, 100%, 40%);">+void soc_enable(struct device *dev);</span><br><span> </span><br><span> #include <arch/acpi.h></span><br><span> void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt);</span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c</span><br><span>index 933a966..0512bcf 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/spi.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/spi.c</span><br><span>@@ -343,7 +343,7 @@</span><br><span> {</span><br><span> int ich_version = 0;</span><br><span> uint8_t bios_cntl;</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> uint32_t ids;</span><br><span> uint16_t vendor_id, device_id;</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c</span><br><span>index 4b109fd..ff1c571 100644</span><br><span>--- a/src/southbridge/intel/fsp_rangeley/watchdog.c</span><br><span>+++ b/src/southbridge/intel/fsp_rangeley/watchdog.c</span><br><span>@@ -25,7 +25,7 @@</span><br><span> </span><br><span> void watchdog_off(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span> u32 value, abase;</span><br><span> </span><br><span> /* Turn off the watchdog. */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26250">change 26250</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If92825f5bdb1399f61b7eba3ae81caa9c264a554 </div>
<div style="display:none"> Gerrit-Change-Number: 26250 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>