[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Get rid of device_t
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Sun May 13 13:03:37 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26247
Change subject: sb/intel/bd82x6x: Get rid of device_t
......................................................................
sb/intel/bd82x6x: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Ib852d41e43f8c3780bb9e016f0c5fbfa91889691
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/bd82x6x/watchdog.c
13 files changed, 51 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/26247/1
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 02165d6..d3d57aa 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -337,7 +337,7 @@
return "HDEF";
}
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index ea7a808..8e9b827 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -107,9 +107,9 @@
* 0x80 - The PIRQ is not routed.
*/
-static void pch_pirq_init(device_t dev)
+static void pch_pirq_init(struct device *dev)
{
- device_t irq_dev;
+ struct device *irq_dev;
/* Interrupt 11 is not used by legacy devices and so can always be used for
PCI interrupts. Full legacy IRQ routing is complicated and hard to
get right. Fortunately all modern OS use MSI and so it's not that big of
@@ -144,7 +144,7 @@
}
}
-static void pch_gpi_routing(device_t dev)
+static void pch_gpi_routing(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -173,7 +173,7 @@
pci_write_config32(dev, GPIO_ROUT, reg32);
}
-static void pch_power_options(device_t dev)
+static void pch_power_options(struct device *dev)
{
u8 reg8;
u16 reg16, pmbase;
@@ -396,7 +396,7 @@
RCBA32(HPTC) = reg32;
}
-static void enable_clock_gating(device_t dev)
+static void enable_clock_gating(struct device *dev)
{
u32 reg32;
u16 reg16;
@@ -561,7 +561,7 @@
pch_spi_init(dev);
}
-static void pch_lpc_read_resources(device_t dev)
+static void pch_lpc_read_resources(struct device *dev)
{
struct resource *res;
config_t *config = dev->chip_info;
@@ -625,13 +625,13 @@
}
}
-static void pch_lpc_enable_resources(device_t dev)
+static void pch_lpc_enable_resources(struct device *dev)
{
pch_decode_init(dev);
return pci_dev_enable_resources(dev);
}
-static void pch_lpc_enable(device_t dev)
+static void pch_lpc_enable(struct device *dev)
{
/* Enable PCH Display Port */
RCBA16(DISPBDF) = 0x0010;
@@ -640,7 +640,7 @@
pch_enable(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -651,7 +651,7 @@
}
}
-static void southbridge_inject_dsdt(device_t dev)
+static void southbridge_inject_dsdt(struct device *dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
@@ -684,7 +684,7 @@
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
int c2_latency;
@@ -819,9 +819,9 @@
return "LPCB";
}
-static void southbridge_fill_ssdt(device_t device)
+static void southbridge_fill_ssdt(struct device *device)
{
- device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index a5c5e52..a17e57c 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -116,7 +116,7 @@
}
#ifndef __SMM__
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -544,7 +544,7 @@
#else /* !__SMM__ */
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -611,7 +611,7 @@
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -641,7 +641,7 @@
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -688,14 +688,14 @@
}
/* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
+static void intel_me_hide(struct device *dev)
{
dev->enabled = 0;
pch_enable(dev);
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
me_bios_path path = intel_me_path(dev);
@@ -737,7 +737,7 @@
}
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 54a16ce..ab02c7b 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -118,7 +118,7 @@
}
#ifndef __SMM__
-static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -524,7 +524,7 @@
#else /* !__SMM__ */
/* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(device_t dev)
+static me_bios_path intel_me_path(struct device *dev)
{
me_bios_path path = ME_DISABLE_BIOS_PATH;
struct me_hfs hfs;
@@ -598,7 +598,7 @@
}
/* Prepare ME for MEI messages */
-static int intel_mei_setup(device_t dev)
+static int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -628,7 +628,7 @@
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(device_t dev)
+static int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -675,14 +675,14 @@
}
/* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
+static void intel_me_hide(struct device *dev)
{
dev->enabled = 0;
pch_enable(dev);
}
/* Check whether ME is present and do basic init */
-static void intel_me_init(device_t dev)
+static void intel_me_init(struct device *dev)
{
me_bios_path path = intel_me_path(dev);
me_bios_payload mbp_data;
@@ -740,7 +740,7 @@
}
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 73c84bb..2608fd4 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -36,7 +36,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
@@ -53,7 +53,7 @@
pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
#else
- device_t dev;
+ struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
@@ -209,9 +209,9 @@
}
/* Check if any port in set X to X+3 is enabled */
-static int pch_pcie_check_set_enabled(device_t dev)
+static int pch_pcie_check_set_enabled(struct device *dev)
{
- device_t port;
+ struct device *port;
int port_func;
int dev_func = PCI_FUNC(dev->path.pci.devfn);
@@ -259,7 +259,7 @@
static void pch_pcie_devicetree_update(
struct southbridge_intel_bd82x6x_config *config)
{
- device_t dev;
+ struct device *dev;
/*
* hotplug map should also be updated along with their
@@ -313,7 +313,7 @@
}
/* Special handling for PCIe Root Port devices */
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
u32 reg32;
@@ -423,7 +423,7 @@
}
}
-void pch_enable(device_t dev)
+void pch_enable(struct device *dev)
{
u32 reg32;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index ebcb058..e8cf811 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -62,7 +62,7 @@
#if !defined(__PRE_RAM__)
#if !defined(__SIMPLE_DEVICE__)
#include "chip.h"
-void pch_enable(device_t dev);
+void pch_enable(struct device *dev);
#endif
int pch_silicon_revision(void);
int pch_silicon_type(void);
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 85e431e..f86d8a01e 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -100,7 +100,7 @@
ich_pci_dev_enable_resources(dev);
}
-static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 1f4c157..1e87838 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -265,13 +265,13 @@
}
}
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
{
/* Power Management init before enumeration */
pch_pcie_pm_early(dev);
}
-static void pch_pciexp_scan_bridge(device_t dev)
+static void pch_pciexp_scan_bridge(struct device *dev)
{
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
@@ -306,7 +306,7 @@
return NULL;
}
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index d4268da..78c5964 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -208,7 +208,7 @@
pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
}
-static void sata_enable(device_t dev)
+static void sata_enable(struct device *dev)
{
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -233,7 +233,7 @@
pci_write_config16(dev, 0x90, map);
}
-static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sata_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -249,7 +249,7 @@
return "SATA";
}
-static void sata_fill_ssdt(device_t dev)
+static void sata_fill_ssdt(struct device *dev)
{
config_t *config = dev->chip_info;
generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 33908905..e8eec4c 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -25,7 +25,7 @@
#include <southbridge/intel/common/smbus.h>
#include "pch.h"
-static void pch_smbus_init(device_t dev)
+static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
@@ -41,7 +41,7 @@
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device *dev, u8 address)
{
u16 device;
struct resource *res;
@@ -54,7 +54,7 @@
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{
u16 device;
struct resource *res;
@@ -72,7 +72,7 @@
.write_byte = lsmbus_write_byte,
};
-static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void smbus_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -87,7 +87,7 @@
.set_subsystem = smbus_set_subsystem,
};
-static void smbus_read_resources(device_t dev)
+static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
res->base = SMBUS_IO_BASE;
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index b5ce820..4822ec5 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -74,7 +74,7 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
u8 access_cntl;
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 6acc63b..9c9d8b5 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -56,7 +56,7 @@
return "XHC";
}
-static void xhci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void xhci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c
index 74f69b0..9a867e4 100644
--- a/src/southbridge/intel/bd82x6x/watchdog.c
+++ b/src/southbridge/intel/bd82x6x/watchdog.c
@@ -28,7 +28,7 @@
//
void watchdog_off(void)
{
- device_t dev;
+ struct device *dev;
unsigned long value, base;
/* Turn off the ICH7 watchdog. */
--
To view, visit https://review.coreboot.org/26247
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib852d41e43f8c3780bb9e016f0c5fbfa91889691
Gerrit-Change-Number: 26247
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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