[coreboot-gerrit] Change in coreboot[master]: stoneyridge: Store wake parameters in NVS

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/26208


Change subject: stoneyridge: Store wake parameters in NVS
......................................................................

stoneyridge: Store wake parameters in NVS

ACPI _SWS needs information on PM1 and ACPI events (though events can be
read directly). Unfortunately PM1 is cleared in normal path and in resume
path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS.

BUG=b:75996437
TEST=Build and boot grunt recording serial. Run suspend stress test, after
3 resumes closed file and examined for the message indicating what was
being saved to NVS. Two different path, normal boot (first boot) and
resume path had different PM1.

Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/common/block/pi/amd_resume_final.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/include/soc/smi.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
5 files changed, 38 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/26208/1

diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c
index a282665..4df4743 100644
--- a/src/soc/amd/common/block/pi/amd_resume_final.c
+++ b/src/soc/amd/common/block/pi/amd_resume_final.c
@@ -15,9 +15,11 @@
 
 #include <bootstate.h>
 #include <amdblocks/agesawrapper_call.h>
+#include <soc/southbridge.h>
 
 static void agesawrapper_s3finalrestore(void *unused)
 {
+	set_nvs_sws();
 	do_agesawrapper(agesawrapper_amds3finalrestore, "amds3finalrestore");
 }
 
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 02ee6fa..492163a 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -278,9 +278,7 @@
 		chromeos_init_vboot(&gnvs->chromeos);
 		gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
 	}
-
-	/* Set unknown wake source */
-	gnvs->pm1i = ~0ULL;
+	set_nvs_sws();
 
 	/* CPU core count */
 	gnvs->pcnt = dev_count_cpu();
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 636f9c3..9498b79f 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -159,6 +159,8 @@
 #define NUMBER_SMITYPES				160
 #define TYPE_TO_MASK(X)				(1 << (X) % 32)
 
+#define SMI_REG_ACPI_EVENT		0x00
+#define SMI_REG_ACPI_EVENT_EN		0x04
 #define SMI_REG_SMISTS0			0x80
 #define SMI_REG_SMISTS1			0x84
 #define SMI_REG_SMISTS2			0x88
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 0a23fca..852b11b 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -493,4 +493,7 @@
 /* Initialize all the i2c buses that are not marked with early init. */
 void i2c_soc_init(void);
 
+/* Copy _SWS variables from IOAPIC scratch registers to nvs */
+void set_nvs_sws(void);
+
 #endif /* __STONEYRIDGE_H__ */
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index eb8820f..33222ef 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -26,12 +26,14 @@
 #include <elog.h>
 #include <amdblocks/amd_pci_util.h>
 #include <soc/southbridge.h>
+#include <soc/northbridge.h> /* needed for IOAPIC scratch register access */
 #include <soc/smi.h>
 #include <soc/amd_pci_int_defs.h>
 #include <fchec.h>
 #include <delay.h>
 #include <soc/pci_devs.h>
 #include <agesa_headers.h>
+#include <soc/nvs.h>
 
 /*
  * Table of devices that need their AOAC registers enabled and waited
@@ -681,14 +683,42 @@
 static void sb_clear_pm1_status(void)
 {
 	uint16_t pm1_sts = reset_pm1_status();
+
+	nb_ioapic_write(NB_IOAPIC_SCRATCH1, (uint32_t)pm1_sts);
 	sb_log_pm1_status(pm1_sts);
 	print_pm1_status(pm1_sts);
 }
 
+static void sb_store_acpi_events(void)
+{
+	uint32_t acpi_event;
+
+	acpi_event = smi_read32(SMI_REG_ACPI_EVENT);
+	acpi_event &= smi_read32(SMI_REG_ACPI_EVENT_EN);
+	nb_ioapic_write(NB_IOAPIC_SCRATCH0, acpi_event);
+}
+
+void set_nvs_sws(void)
+{
+	struct global_nvs_t *gnvs;
+
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+	if (gnvs != NULL) {
+		gnvs->pm1i = (uint64_t)nb_ioapic_read(NB_IOAPIC_SCRATCH1);
+		gnvs->gpei = (uint64_t)nb_ioapic_read(NB_IOAPIC_SCRATCH0);
+
+		printk(BIOS_DEBUG, "Loaded _SWS parameters PM1 0x%08x,"
+				" EVENT 0x%08x into nvs\n",
+				nb_ioapic_read(NB_IOAPIC_SCRATCH1),
+				nb_ioapic_read(NB_IOAPIC_SCRATCH0));
+	}
+}
+
 void southbridge_init(void *chip_info)
 {
 	sb_init_acpi_ports();
 	sb_clear_pm1_status();
+	sb_store_acpi_events();
 }
 
 void southbridge_final(void *chip_info)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5
Gerrit-Change-Number: 26208
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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