<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26208">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">stoneyridge: Store wake parameters in NVS<br><br>ACPI _SWS needs information on PM1 and ACPI events (though events can be<br>read directly). Unfortunately PM1 is cleared in normal path and in resume<br>path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS.<br><br>BUG=b:75996437<br>TEST=Build and boot grunt recording serial. Run suspend stress test, after<br>3 resumes closed file and examined for the message indicating what was<br>being saved to NVS. Two different path, normal boot (first boot) and<br>resume path had different PM1.<br><br>Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/common/block/pi/amd_resume_final.c<br>M src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>5 files changed, 38 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/26208/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c</span><br><span>index a282665..4df4743 100644</span><br><span>--- a/src/soc/amd/common/block/pi/amd_resume_final.c</span><br><span>+++ b/src/soc/amd/common/block/pi/amd_resume_final.c</span><br><span>@@ -15,9 +15,11 @@</span><br><span> </span><br><span> #include <bootstate.h></span><br><span> #include <amdblocks/agesawrapper_call.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/southbridge.h></span><br><span> </span><br><span> static void agesawrapper_s3finalrestore(void *unused)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ set_nvs_sws();</span><br><span> do_agesawrapper(agesawrapper_amds3finalrestore, "amds3finalrestore");</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c</span><br><span>index 02ee6fa..492163a 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi.c</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi.c</span><br><span>@@ -278,9 +278,7 @@</span><br><span> chromeos_init_vboot(&gnvs->chromeos);</span><br><span> gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;</span><br><span> }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set unknown wake source */</span><br><span style="color: hsl(0, 100%, 40%);">- gnvs->pm1i = ~0ULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ set_nvs_sws();</span><br><span> </span><br><span> /* CPU core count */</span><br><span> gnvs->pcnt = dev_count_cpu();</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h</span><br><span>index 636f9c3..9498b79f 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/smi.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h</span><br><span>@@ -159,6 +159,8 @@</span><br><span> #define NUMBER_SMITYPES 160</span><br><span> #define TYPE_TO_MASK(X) (1 << (X) % 32)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_REG_ACPI_EVENT 0x00</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMI_REG_ACPI_EVENT_EN 0x04</span><br><span> #define SMI_REG_SMISTS0 0x80</span><br><span> #define SMI_REG_SMISTS1 0x84</span><br><span> #define SMI_REG_SMISTS2 0x88</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index 0a23fca..852b11b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -493,4 +493,7 @@</span><br><span> /* Initialize all the i2c buses that are not marked with early init. */</span><br><span> void i2c_soc_init(void);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+/* Copy _SWS variables from IOAPIC scratch registers to nvs */</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nvs_sws(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #endif /* __STONEYRIDGE_H__ */</span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index eb8820f..33222ef 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -26,12 +26,14 @@</span><br><span> #include <elog.h></span><br><span> #include <amdblocks/amd_pci_util.h></span><br><span> #include <soc/southbridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/northbridge.h> /* needed for IOAPIC scratch register access */</span><br><span> #include <soc/smi.h></span><br><span> #include <soc/amd_pci_int_defs.h></span><br><span> #include <fchec.h></span><br><span> #include <delay.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <agesa_headers.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/nvs.h></span><br><span> </span><br><span> /*</span><br><span> * Table of devices that need their AOAC registers enabled and waited</span><br><span>@@ -681,14 +683,42 @@</span><br><span> static void sb_clear_pm1_status(void)</span><br><span> {</span><br><span> uint16_t pm1_sts = reset_pm1_status();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ nb_ioapic_write(NB_IOAPIC_SCRATCH1, (uint32_t)pm1_sts);</span><br><span> sb_log_pm1_status(pm1_sts);</span><br><span> print_pm1_status(pm1_sts);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void sb_store_acpi_events(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t acpi_event;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_event = smi_read32(SMI_REG_ACPI_EVENT);</span><br><span style="color: hsl(120, 100%, 40%);">+ acpi_event &= smi_read32(SMI_REG_ACPI_EVENT_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ nb_ioapic_write(NB_IOAPIC_SCRATCH0, acpi_event);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void set_nvs_sws(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct global_nvs_t *gnvs;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gnvs != NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->pm1i = (uint64_t)nb_ioapic_read(NB_IOAPIC_SCRATCH1);</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->gpei = (uint64_t)nb_ioapic_read(NB_IOAPIC_SCRATCH0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Loaded _SWS parameters PM1 0x%08x,"</span><br><span style="color: hsl(120, 100%, 40%);">+ " EVENT 0x%08x into nvs\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ nb_ioapic_read(NB_IOAPIC_SCRATCH1),</span><br><span style="color: hsl(120, 100%, 40%);">+ nb_ioapic_read(NB_IOAPIC_SCRATCH0));</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void southbridge_init(void *chip_info)</span><br><span> {</span><br><span> sb_init_acpi_ports();</span><br><span> sb_clear_pm1_status();</span><br><span style="color: hsl(120, 100%, 40%);">+ sb_store_acpi_events();</span><br><span> }</span><br><span> </span><br><span> void southbridge_final(void *chip_info)</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26208">change 26208</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5 </div>
<div style="display:none"> Gerrit-Change-Number: 26208 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>