[coreboot-gerrit] Change in coreboot[master]: mainboard/asus/am1i-a: get the TPM working
Kevin Cody-Little (Code Review)
gerrit at coreboot.org
Wed May 9 16:54:21 CEST 2018
Kevin Cody-Little has uploaded this change for review. ( https://review.coreboot.org/26193
Change subject: mainboard/asus/am1i-a: get the TPM working
......................................................................
mainboard/asus/am1i-a: get the TPM working
There were no PNP or ACPI entries for the LPC TPM, so although the
header was active and LPC worked over it, Linux would not see the
actual TPM chip attached thereto.
Tested with ASUS's TPM/FW 3.19 module and the trousers tools.
Repairs were somewhat involved:
Add PNP entry for the LPC TPM to the board's devicetree.cb.
Add Kconfig entry to indicate the mainboard has an LPC TPM.
Add ACPI name functions to southbridge/amd/agesa/hudson/lpc.c and
to northbridge/amd/agesa/family16kb/northbridge.c so that the TPM
would register itself to the correct namespace; otherwise turning
on TPM breaks the ACPI tables, and the payload won't find SATA.
Alter the pc80/tpm/tis.c driver to get is port value from PNP; it
was previously hardcoded to 2e, where the SuperIO is.
Add the init_tpm() call to drivers/amd/agesa/romstage.c
Change-Id: I8c1aea245f81fa44a6bdd5301bbee958cbcdfaaa
Signed-off-by: Kevin Cody-Little <kcodyjr at gmail.com>
---
M src/drivers/amd/agesa/romstage.c
M src/drivers/pc80/tpm/tis.c
M src/mainboard/asus/am1i-a/Kconfig
M src/mainboard/asus/am1i-a/devicetree.cb
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/southbridge/amd/agesa/hudson/lpc.c
6 files changed, 37 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/26193/1
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
index 197a007..4c319e6 100644
--- a/src/drivers/amd/agesa/romstage.c
+++ b/src/drivers/amd/agesa/romstage.c
@@ -29,6 +29,10 @@
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/state_machine.h>
+#if IS_ENABLED(CONFIG_LPC_TPM)
+#include <security/tpm/tis.h>
+#endif
+
#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
#error "Only EARLY_CBMEM_INIT is supported."
#endif
@@ -112,6 +116,10 @@
romstage_handoff_init(cb->s3resume);
+#if IS_ENABLED(CONFIG_LPC_TPM)
+ init_tpm(cb->s3resume);
+#endif
+
postcar_frame_init(&pcf, HIGH_ROMSTAGE_STACK_SIZE);
recover_postcar_frame(&pcf, cb->s3resume);
diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
index 714b7e5..3549173 100644
--- a/src/drivers/pc80/tpm/tis.c
+++ b/src/drivers/pc80/tpm/tis.c
@@ -904,11 +904,13 @@
else
acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_OFF);
+ u16 port = dev->path.pnp.port;
+
/* Resources */
acpigen_write_name("_CRS");
acpigen_write_resourcetemplate_header();
acpigen_write_mem32fixed(1, CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000);
- acpigen_write_io16(0x2e, 0x2e, 1, 2, 1);
+ acpigen_write_io16(port, port, 1, 2, 1);
if (CONFIG_TPM_PIRQ) {
/*
diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig
index e0a78ff..56d5d0c 100644
--- a/src/mainboard/asus/am1i-a/Kconfig
+++ b/src/mainboard/asus/am1i-a/Kconfig
@@ -16,6 +16,7 @@
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE
select SUPERIO_ITE_IT8623E
+ select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR
string
diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb
index b810487..4fcd13e 100644
--- a/src/mainboard/asus/am1i-a/devicetree.cb
+++ b/src/mainboard/asus/am1i-a/devicetree.cb
@@ -85,6 +85,9 @@
io 0x62 = 0x300
end
end #superio/ite/it8623e
+ chip drivers/pc80/tpm
+ device pnp 4e.0 on end # TPM module
+ end
end #device pci 14.3 # LPC
device pci 14.7 off end # SD - no card reader present
end #chip southbridge/amd/agesa/hudson
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index f667f6f..8e5e472 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -795,11 +795,20 @@
}
}
+static const char *domain_acpi_name(const struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ return NULL;
+}
+
static struct device_operations pci_domain_ops = {
.read_resources = domain_read_resources,
.set_resources = domain_set_resources,
.init = DEVICE_NOOP,
.scan_bus = pci_domain_scan_bus,
+ .acpi_name = domain_acpi_name,
};
static void sysconf_init(device_t dev) // first node
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 1166054..7ada832 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -29,6 +29,7 @@
#include <pc80/i8254.h>
#include <pc80/i8259.h>
#include "hudson.h"
+#include "pci_devs.h"
static void lpc_init(device_t dev)
{
@@ -318,6 +319,17 @@
hudson_lpc_enable_childrens_resources(dev);
}
+static const char *lpc_acpi_name(const struct device *dev)
+{
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ if (dev->path.pci.devfn == LPC_DEVFN)
+ return "LIBR";
+
+ return NULL;
+}
+
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
@@ -338,6 +350,7 @@
.init = lpc_init,
.scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
+ .acpi_name = lpc_acpi_name,
};
static const struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops,
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8c1aea245f81fa44a6bdd5301bbee958cbcdfaaa
Gerrit-Change-Number: 26193
Gerrit-PatchSet: 1
Gerrit-Owner: Kevin Cody-Little <kcodyjr at gmail.com>
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