[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Move tco common functions into block/smbus
Subrata Banik (Code Review)
gerrit at coreboot.org
Tue May 8 11:08:38 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26166
Change subject: soc/intel/common/block: Move tco common functions into block/smbus
......................................................................
soc/intel/common/block: Move tco common functions into block/smbus
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/smbus.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/elog.c
M src/soc/intel/apollolake/include/soc/iomap.h
M src/soc/intel/apollolake/include/soc/pm.h
A src/soc/intel/apollolake/include/soc/smbus.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/cannonlake/include/soc/smbus.h
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/cannonlake/romstage/power_state.c
M src/soc/intel/common/block/include/intelblocks/pmclib.h
A src/soc/intel/common/block/include/intelblocks/tco.h
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/smbus/Kconfig
M src/soc/intel/common/block/smbus/Makefile.inc
A src/soc/intel/common/block/smbus/tco.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/include/soc/iomap.h
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/include/soc/smbus.h
M src/soc/intel/skylake/pmutil.c
26 files changed, 255 insertions(+), 184 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/26166/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 0f1f121..79d57e5 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -90,6 +90,7 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_TIMER
+ select SOC_INTEL_COMMON_BLOCK_TCO
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 2e17979..f7f2bf6 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -25,6 +25,7 @@
#include <intelblocks/rtc.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/tco.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/gpio.h>
@@ -86,8 +87,6 @@
void bootblock_soc_early_init(void)
{
- uint32_t reg;
-
enable_pmcbar();
/* Clear global reset promotion bit */
@@ -110,9 +109,7 @@
pmc_gpe_init();
/* Stop TCO timer */
- reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
- reg |= TCO_TMR_HLT;
- outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
+ tco_timer_disable();
/* Use Nx and paging to prevent the frontend from writing back dirty
* cache-as-ram lines to backing store that doesn't exist when the L1I
diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c
index 1e9b7d8..9813628 100644
--- a/src/soc/intel/apollolake/elog.c
+++ b/src/soc/intel/apollolake/elog.c
@@ -20,6 +20,7 @@
#include <elog.h>
#include <soc/pm.h>
#include <soc/pci_devs.h>
+#include <soc/smbus.h>
#include <stdint.h>
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
@@ -78,7 +79,7 @@
/* TCO Timeout */
if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco_sts & TCO_TIMEOUT)
+ ps->tco1_sts & TCO_TIMEOUT)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 9a2500c..30c7d29 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -29,6 +29,9 @@
#define ACPI_BASE_SIZE 0x100
#define R_ACPI_PM1_TMR 0x8
+#define TCO_BASE_ADDRESS ACPI_BASE_ADDRESS
+#define TCO_BASE_SIZE 0x20
+
/* CST Range (R/W) IO port block size */
#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5
/* ACPI PMIO Offset to C-state register*/
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index e8ec645..38f814b 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -132,10 +132,6 @@
#define GPE_CNTL 0x50
#define DEVACT_STS 0x4c
-#define TCO_STS 0x64
-#define TCO_TIMEOUT (1 << 3)
-#define TCO1_CNT 0x68
-#define TCO_TMR_HLT (1 << 11)
#define GPE0_REG_MAX 4
#define GPE0_REG_SIZE 32
@@ -240,7 +236,8 @@
uint32_t pm1_cnt;
uint32_t gpe0_sts[GPE0_REG_MAX];
uint32_t gpe0_en[GPE0_REG_MAX];
- uint32_t tco_sts;
+ uint16_t tco1_sts;
+ uint16_t tco2_sts;
uint32_t prsts;
uint32_t gen_pmcon1;
uint32_t gen_pmcon2;
diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h
new file mode 100644
index 0000000..50f40a3
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/smbus.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_APOLLOLAKE_SMBUS_H_
+#define _SOC_APOLLOLAKE_SMBUS_H_
+
+/* PCI registers */
+#define TCOBASE 0x50 /* TCO base address. */
+#define TCOCTL 0x54
+#define TCO_BASE_EN (1 << 8) /* TCO base enable. */
+
+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
+#define TCO1_STS 0x04
+#define TCO_TIMEOUT (1 << 3)
+#define TCO2_STS 0x06
+#define TCO2_STS_SECOND_TO (1 << 1)
+#define TCO2_STS_BOOT (1 << 2)
+#define TCO1_CNT 0x08
+#define TCO_LOCK (1 << 12)
+#define TCO_TMR_HLT (1 << 11)
+
+#endif
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 05590bd..00b1d1c 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -28,11 +28,13 @@
#include <intelblocks/msr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
+#include <intelblocks/tco.h>
#include <rules.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
+#include <soc/smbus.h>
#include <timer.h>
#include <security/vboot/vbnv.h>
#include "chip.h"
@@ -133,15 +135,6 @@
return gpe_sts_bits;
}
-uint32_t soc_reset_tco_status(void)
-{
- uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
- uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
-
- outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS);
- return tco_sts & tco_en;
-}
-
void soc_clear_pm_registers(uintptr_t pmc_bar)
{
uint32_t gen_pmcon1;
@@ -173,14 +166,18 @@
{
uintptr_t pmc_bar0 = read_pmc_mmio_bar();
- ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
+ ps->tco1_sts = tco_read_reg(TCO1_STS);
+ ps->tco2_sts = tco_read_reg(TCO2_STS);
+
ps->prsts = read32((void *)(pmc_bar0 + PRSTS));
ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));
ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));
ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));
- printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",
- ps->prsts, ps->tco_sts);
+ printk(BIOS_DEBUG, "prsts: %08x\n",
+ ps->prsts);
+ printk(BIOS_DEBUG, "tco_sts: %04x %04x\n",
+ ps->tco1_sts, ps->tco2_sts);
printk(BIOS_DEBUG,
"gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",
ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 662f29d..92983ff 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -71,6 +71,8 @@
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_SPI
+ select SOC_INTEL_COMMON_BLOCK_TCO
+ select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XDCI
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a2e6352..3eedd64 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -23,6 +23,7 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
@@ -45,8 +46,6 @@
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_TCOBASE 0x2778
-#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
@@ -111,35 +110,6 @@
}
}
-static void soc_config_tco(void)
-{
- uint32_t reg32;
- uint16_t tcobase;
- uint16_t tcocnt;
-
- /* Disable TCO in SMBUS Device first before changing Base Address */
- reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
- reg32 &= ~TCO_BASE_EN;
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
-
- /* Program TCO Base */
- tcobase = TCO_BASE_ADDRESS;
- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase);
-
- /* Enable TCO in SMBUS */
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN);
-
- /*
- * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
- */
- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
-
- /* Program TCO timer halt */
- tcocnt = inw(tcobase + TCO1_CNT);
- tcocnt |= TCO_TMR_HLT;
- outw(tcocnt, tcobase + TCO1_CNT);
-}
-
void pch_early_iorange_init(void)
{
uint16_t dec_rng, dec_en = 0;
@@ -171,7 +141,7 @@
soc_config_acpibase();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
- soc_config_tco();
+ tco_enable_bar();
/* Program SMBUS_BASE_ADDRESS and Enable it */
smbus_common_init();
diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 5216460..2e8468a 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
+#include <intelblocks/tco.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <soc/p2sb.h>
@@ -55,17 +56,11 @@
{
device_t dev;
uint32_t reg32;
- uint16_t tcobase, tcocnt;
uint8_t *pmcbase;
config_t *config;
uint8_t reg8;
- /* TCO Lock down */
- tcobase = smbus_tco_regs();
- tcocnt = inw(tcobase + TCO1_CNT);
- tcocnt |= TCO_LOCK;
- outw(tcocnt, tcobase + TCO1_CNT);
-
+ tco_lockdown();
/*
* Disable ACPI PM timer based on dt policy
*
diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h
index 9f1cf34..cf2eae8 100644
--- a/src/soc/intel/cannonlake/include/soc/smbus.h
+++ b/src/soc/intel/cannonlake/include/soc/smbus.h
@@ -33,6 +33,7 @@
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1)
+#define TCO2_STS_BOOT (1 << 2)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 4db4d63..df8ecdc 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -29,6 +29,7 @@
#include <console/console.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
+#include <intelblocks/tco.h>
#include <halt.h>
#include <rules.h>
#include <stdlib.h>
@@ -154,38 +155,6 @@
return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;
}
-uint16_t smbus_tco_regs(void)
-{
- uint16_t reg16;
-
- reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
-
- return ALIGN_DOWN(reg16, 0x20);
-}
-
-uint32_t soc_reset_tco_status(void)
-{
- u16 tco1_sts;
- u16 tco2_sts;
- u16 tcobase;
-
- tcobase = smbus_tco_regs();
-
- /* TCO Status 2 register */
- tco2_sts = inw(tcobase + TCO2_STS);
- tco2_sts |= TCO2_STS_SECOND_TO;
- outw(tco2_sts, tcobase + TCO2_STS);
-
- /* TCO Status 1 register */
- tco1_sts = inw(tcobase + TCO1_STS);
-
- /* Clear SECOND_TO_STS bit */
- if (tco2_sts & TCO2_STS_SECOND_TO)
- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
-
- return (tco2_sts << 16) | tco1_sts;
-}
-
uintptr_t soc_read_pmc_base(void)
{
return (uintptr_t)pmc_mmio_regs();
diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c
index b62e5fd..1df60e0 100644
--- a/src/soc/intel/cannonlake/romstage/power_state.c
+++ b/src/soc/intel/cannonlake/romstage/power_state.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <device/device.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/tco.h>
#include <string.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -75,13 +76,10 @@
void soc_fill_power_state(struct chipset_power_state *ps)
{
- uint16_t tcobase;
uint8_t *pmc;
- tcobase = smbus_tco_regs();
-
- ps->tco1_sts = inw(tcobase + TCO1_STS);
- ps->tco2_sts = inw(tcobase + TCO2_STS);
+ ps->tco1_sts = tco_read_reg(TCO1_STS);
+ ps->tco2_sts = tco_read_reg(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
ps->tco1_sts, ps->tco2_sts);
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index d631f01..87feb05 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -93,13 +93,6 @@
*/
const char * const *soc_tco_sts_array(size_t *a);
-/*
- * Resets the tco status registers. This function clears the tco_sts register
- * and returns the sts and enable bits set.
- */
-uint32_t soc_reset_tco_status(void);
-
-
/* GPE */
/*
diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h
new file mode 100644
index 0000000..7d4683c
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/tco.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_TCO_H
+#define SOC_INTEL_COMMON_BLOCK_TCO_H
+
+/* Stop TCO timer */
+void tco_timer_disable(void);
+/* Enable TCO BAR using SMBUS TCO base to access TCO related register */
+void tco_enable_bar(void);
+
+void tco_lockdown(void);
+/*
+ * Resets the tco status registers. This function clears the tco_sts register
+ * and returns the sts and enable bits set.
+ */
+uint32_t tco_reset_status(void);
+uint16_t tco_read_reg(uint16_t tco_reg);
+void tco_write_reg(uint16_t tco_reg, uint16_t value);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 38d4196..246dab1 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -21,6 +21,7 @@
#include <halt.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/gpio.h>
+#include <intelblocks/tco.h>
#include <soc/pm.h>
#include <string.h>
#include <timer.h>
@@ -249,7 +250,7 @@
uint32_t pmc_clear_tco_status(void)
{
- return print_tco_status(soc_reset_tco_status());
+ return print_tco_status(tco_reset_status());
}
/* GPE */
diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig
index 4514383..1d22998 100644
--- a/src/soc/intel/common/block/smbus/Kconfig
+++ b/src/soc/intel/common/block/smbus/Kconfig
@@ -2,3 +2,14 @@
bool
help
Intel Processor common SMBus support
+
+config SOC_INTEL_COMMON_BLOCK_TCO
+ bool
+ help
+ Intel Processor common TCO support
+
+config SOC_INTEL_COMMON_BLOCK_TCO_ENABLE
+ bool
+ depends on SOC_INTEL_COMMON_BLOCK_TCO
+ help
+ Select this config to enable TCO BAR through SMBUS
diff --git a/src/soc/intel/common/block/smbus/Makefile.inc b/src/soc/intel/common/block/smbus/Makefile.inc
index 1a10fd9..309ad9a 100644
--- a/src/soc/intel/common/block/smbus/Makefile.inc
+++ b/src/soc/intel/common/block/smbus/Makefile.inc
@@ -1,8 +1,15 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
+
+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
new file mode 100644
index 0000000..02783a0
--- /dev/null
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/tco.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/smbus.h>
+
+#define PCR_DMI_TCOBASE 0x2778
+/* Enable TCO I/O range decode. */
+#define TCOEN (1 << 1)
+
+/* Get base address of TCO I/O registers. */
+static uint16_t tco_get_bar(void)
+{
+ return TCO_BASE_ADDRESS;
+}
+
+uint16_t tco_read_reg(uint16_t tco_reg)
+{
+ uint16_t tcobase;
+
+ tcobase = tco_get_bar();
+
+ return inw(tcobase + tco_reg);
+}
+
+void tco_write_reg(uint16_t tco_reg, uint16_t value)
+{
+ uint16_t tcobase;
+
+ tcobase = tco_get_bar();
+
+ outw(value, tcobase + tco_reg);
+}
+
+void tco_lockdown(void)
+{
+ uint16_t tcocnt;
+
+ /* TCO Lock down */
+ tcocnt = tco_read_reg(TCO1_CNT);
+ tcocnt |= TCO_LOCK;
+ tco_write_reg(TCO1_CNT, tcocnt);
+}
+
+uint32_t tco_reset_status(void)
+{
+ uint16_t tco1_sts;
+ uint16_t tco2_sts;
+
+ /* TCO Status 2 register */
+ tco2_sts = tco_read_reg(TCO2_STS);
+ tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
+ tco_write_reg(TCO2_STS, tco2_sts);
+
+ /* TCO Status 1 register */
+ tco1_sts = tco_read_reg(TCO1_STS);
+
+ /* Clear SECOND_TO_STS bit */
+ if (tco2_sts & TCO2_STS_SECOND_TO)
+ tco_write_reg(TCO2_STS, tco2_sts & ~TCO2_STS_SECOND_TO);
+
+ return (tco2_sts << 16) | tco1_sts;
+}
+
+void tco_timer_disable(void)
+{
+ uint16_t tcocnt;
+
+ /* Program TCO timer halt */
+ tcocnt = tco_read_reg(TCO1_CNT);
+ tcocnt |= TCO_TMR_HLT;
+ tco_write_reg(TCO1_CNT, tcocnt);
+}
+
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE)
+void tco_enable_bar(void)
+{
+ uint32_t reg32;
+ uint16_t tcobase;
+#if defined(__SIMPLE_DEVICE__)
+ int devfn = PCH_DEVFN_SMBUS;
+ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
+#else
+ struct device *dev;
+ dev = PCH_DEV_SMBUS;
+#endif
+
+ /* Disable TCO in SMBUS Device first before changing Base Address */
+ reg32 = pci_read_config32(dev, TCOCTL);
+ reg32 &= ~TCO_BASE_EN;
+ pci_write_config32(dev, TCOCTL, reg32);
+
+ /* Program TCO Base */
+ tcobase = tco_get_bar();
+ pci_write_config32(dev, TCOBASE, tcobase);
+
+ /* Enable TCO in SMBUS */
+ pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN);
+
+ /*
+ * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
+ */
+ pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);
+
+ tco_timer_disable();
+}
+#endif
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 8ed7239..cdd26da 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -31,6 +31,7 @@
#include <soc/pm.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
+#include <soc/smbus.h>
#include <spi-generic.h>
#include <stdint.h>
#include <stdlib.h>
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 5fbd57b..a42f87c 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -86,6 +86,8 @@
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_TIMER
+ select SOC_INTEL_COMMON_BLOCK_TCO
+ select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_VMX
select SOC_INTEL_COMMON_BLOCK_XDCI
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 0856ee2..1b5b8b4 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -27,6 +27,7 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/p2sb.h>
@@ -43,7 +44,6 @@
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
#define PCR_DMI_PMBASEC 0x27B0
-#define PCR_DMI_TCOBASE 0x2778
void bootblock_pch_early_init(void)
{
@@ -111,37 +111,6 @@
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
}
-static void soc_config_tco(void)
-{
- uint32_t reg32 = 0;
- uint16_t tcobase;
- uint16_t tcocnt;
-
- /* Disable TCO in SMBUS Device first before changing Base Address */
- reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);
- reg32 &= ~TCO_EN;
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);
-
- /* Program TCO Base */
- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);
-
- /* Enable TCO in SMBUS */
- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);
-
- /*
- * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]
- * to [SMBUS PCI offset 50h[15:5], 1].
- */
- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));
-
- /* Program TCO timer halt */
- tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
- tcobase &= ~0x1f;
- tcocnt = inw(tcobase + TCO1_CNT);
- tcocnt |= TCO_TMR_HLT;
- outw(tcocnt, tcobase + TCO1_CNT);
-}
-
static int pch_check_decode_enable(void)
{
uint32_t dmi_control;
@@ -195,7 +164,7 @@
soc_config_pwrmbase();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
- soc_config_tco();
+ tco_enable_bar();
/* Program SMBUS_BASE_ADDRESS and Enable it */
smbus_common_init();
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index f2fde71..475d79d 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -87,7 +87,7 @@
#define ACPI_BASE_ADDRESS 0x1800
#define ACPI_BASE_SIZE 0x100
-#define TCO_BASE_ADDDRESS 0x400
+#define TCO_BASE_ADDRESS 0x400
#define TCO_BASE_SIZE 0x20
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index 11585a1..5902e82 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -184,9 +184,6 @@
/* Get base address PMC memory mapped registers. */
uint8_t *pmc_mmio_regs(void);
-/* Get base address of TCO I/O registers. */
-uint16_t smbus_tco_regs(void);
-
/* Set the DISB after DRAM init */
void pmc_set_disb(void);
diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h
index aeaf1d9..d725269 100644
--- a/src/soc/intel/skylake/include/soc/smbus.h
+++ b/src/soc/intel/skylake/include/soc/smbus.h
@@ -25,7 +25,7 @@
/* SMBUS TCO base address. */
#define TCOBASE 0x50
#define TCOCTL 0x54
-#define TCO_EN (1 << 8)
+#define TCO_BASE_EN (1 << 8)
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index d05c812..22e2990 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -30,6 +30,7 @@
#include <intelblocks/pmclib.h>
#include <halt.h>
#include <intelblocks/lpc_lib.h>
+#include <intelblocks/tco.h>
#include <rules.h>
#include <stdlib.h>
#include <soc/gpe.h>
@@ -170,40 +171,6 @@
return (void *)(uintptr_t) reg32;
}
-uint16_t smbus_tco_regs(void)
-{
- uint16_t reg16;
-
- reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);
-
- reg16 &= ~0x1f;
-
- return reg16;
-}
-
-uint32_t soc_reset_tco_status(void)
-{
- u16 tco1_sts;
- u16 tco2_sts;
- u16 tcobase;
-
- tcobase = smbus_tco_regs();
-
- /* TCO Status 2 register */
- tco2_sts = inw(tcobase + TCO2_STS);
- tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
- outw(tco2_sts, tcobase + TCO2_STS);
-
- /* TCO Status 1 register */
- tco1_sts = inw(tcobase + TCO1_STS);
-
- /* Clear SECOND_TO_STS bit */
- if (tco2_sts & TCO2_STS_SECOND_TO)
- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
-
- return (tco2_sts << 16) | tco1_sts;
-}
-
uintptr_t soc_read_pmc_base(void)
{
return (uintptr_t) (pmc_mmio_regs());
@@ -283,13 +250,10 @@
void soc_fill_power_state(struct chipset_power_state *ps)
{
- uint16_t tcobase;
uint8_t *pmc;
- tcobase = smbus_tco_regs();
-
- ps->tco1_sts = inw(tcobase + TCO1_STS);
- ps->tco2_sts = inw(tcobase + TCO2_STS);
+ ps->tco1_sts = tco_read_reg(TCO1_STS);
+ ps->tco2_sts = tco_read_reg(TCO2_STS);
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
ps->tco1_sts, ps->tco2_sts);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Gerrit-Change-Number: 26166
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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