<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26166">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Move tco common functions into block/smbus<br><br>This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving<br>common soc code into common/block/smbus.<br><br>BUG=b:78109109<br>BRANCH=none<br>TEST=Build and boot KBL/CNL/APL platform.<br><br>Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/apollolake/bootblock/bootblock.c<br>M src/soc/intel/apollolake/elog.c<br>M src/soc/intel/apollolake/include/soc/iomap.h<br>M src/soc/intel/apollolake/include/soc/pm.h<br>A src/soc/intel/apollolake/include/soc/smbus.h<br>M src/soc/intel/apollolake/pmutil.c<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/bootblock/pch.c<br>M src/soc/intel/cannonlake/finalize.c<br>M src/soc/intel/cannonlake/include/soc/smbus.h<br>M src/soc/intel/cannonlake/pmutil.c<br>M src/soc/intel/cannonlake/romstage/power_state.c<br>M src/soc/intel/common/block/include/intelblocks/pmclib.h<br>A src/soc/intel/common/block/include/intelblocks/tco.h<br>M src/soc/intel/common/block/pmc/pmclib.c<br>M src/soc/intel/common/block/smbus/Kconfig<br>M src/soc/intel/common/block/smbus/Makefile.inc<br>A src/soc/intel/common/block/smbus/tco.c<br>M src/soc/intel/common/block/smm/smihandler.c<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/bootblock/pch.c<br>M src/soc/intel/skylake/include/soc/iomap.h<br>M src/soc/intel/skylake/include/soc/pm.h<br>M src/soc/intel/skylake/include/soc/smbus.h<br>M src/soc/intel/skylake/pmutil.c<br>26 files changed, 255 insertions(+), 184 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/26166/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig</span><br><span>index 0f1f121..79d57e5 100644</span><br><span>--- a/src/soc/intel/apollolake/Kconfig</span><br><span>+++ b/src/soc/intel/apollolake/Kconfig</span><br><span>@@ -90,6 +90,7 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_SA</span><br><span> select SOC_INTEL_COMMON_BLOCK_SCS</span><br><span> select SOC_INTEL_COMMON_BLOCK_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_TCO</span><br><span> select SOC_INTEL_COMMON_BLOCK_UART</span><br><span> select SOC_INTEL_COMMON_BLOCK_XDCI</span><br><span> select SOC_INTEL_COMMON_BLOCK_XHCI</span><br><span>diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>index 2e17979..f7f2bf6 100644</span><br><span>--- a/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>+++ b/src/soc/intel/apollolake/bootblock/bootblock.c</span><br><span>@@ -25,6 +25,7 @@</span><br><span> #include <intelblocks/rtc.h></span><br><span> #include <intelblocks/systemagent.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/gpio.h></span><br><span>@@ -86,8 +87,6 @@</span><br><span> </span><br><span> void bootblock_soc_early_init(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> enable_pmcbar();</span><br><span> </span><br><span> /* Clear global reset promotion bit */</span><br><span>@@ -110,9 +109,7 @@</span><br><span> pmc_gpe_init();</span><br><span> </span><br><span> /* Stop TCO timer */</span><br><span style="color: hsl(0, 100%, 40%);">- reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- reg |= TCO_TMR_HLT;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_timer_disable();</span><br><span> </span><br><span> /* Use Nx and paging to prevent the frontend from writing back dirty</span><br><span> * cache-as-ram lines to backing store that doesn't exist when the L1I</span><br><span>diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c</span><br><span>index 1e9b7d8..9813628 100644</span><br><span>--- a/src/soc/intel/apollolake/elog.c</span><br><span>+++ b/src/soc/intel/apollolake/elog.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <elog.h></span><br><span> #include <soc/pm.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span> #include <stdint.h></span><br><span> </span><br><span> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)</span><br><span>@@ -78,7 +79,7 @@</span><br><span> </span><br><span> /* TCO Timeout */</span><br><span> if (ps->prev_sleep_state != ACPI_S3 &&</span><br><span style="color: hsl(0, 100%, 40%);">- ps->tco_sts & TCO_TIMEOUT)</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco1_sts & TCO_TIMEOUT)</span><br><span> elog_add_event(ELOG_TYPE_TCO_RESET);</span><br><span> </span><br><span> /* Power Button Override */</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>index 9a2500c..30c7d29 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/iomap.h</span><br><span>@@ -29,6 +29,9 @@</span><br><span> #define ACPI_BASE_SIZE 0x100</span><br><span> #define R_ACPI_PM1_TMR 0x8</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_ADDRESS ACPI_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_SIZE 0x20</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* CST Range (R/W) IO port block size */</span><br><span> #define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5</span><br><span> /* ACPI PMIO Offset to C-state register*/</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h</span><br><span>index e8ec645..38f814b 100644</span><br><span>--- a/src/soc/intel/apollolake/include/soc/pm.h</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/pm.h</span><br><span>@@ -132,10 +132,6 @@</span><br><span> </span><br><span> #define GPE_CNTL 0x50</span><br><span> #define DEVACT_STS 0x4c</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCO_STS 0x64</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCO_TIMEOUT (1 << 3)</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCO1_CNT 0x68</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCO_TMR_HLT (1 << 11)</span><br><span> </span><br><span> #define GPE0_REG_MAX 4</span><br><span> #define GPE0_REG_SIZE 32</span><br><span>@@ -240,7 +236,8 @@</span><br><span> uint32_t pm1_cnt;</span><br><span> uint32_t gpe0_sts[GPE0_REG_MAX];</span><br><span> uint32_t gpe0_en[GPE0_REG_MAX];</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t tco_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tco1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tco2_sts;</span><br><span> uint32_t prsts;</span><br><span> uint32_t gen_pmcon1;</span><br><span> uint32_t gen_pmcon2;</span><br><span>diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h</span><br><span>new file mode 100644</span><br><span>index 0000000..50f40a3</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/smbus.h</span><br><span>@@ -0,0 +1,34 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_APOLLOLAKE_SMBUS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_APOLLOLAKE_SMBUS_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* PCI registers */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOBASE 0x50 /* TCO base address. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOCTL 0x54</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_EN (1 << 8) /* TCO base enable. */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO1_STS 0x04</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_TIMEOUT (1 << 3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO2_STS 0x06</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO2_STS_SECOND_TO (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO2_STS_BOOT (1 << 2)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO1_CNT 0x08</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_LOCK (1 << 12)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_TMR_HLT (1 << 11)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c</span><br><span>index 05590bd..00b1d1c 100644</span><br><span>--- a/src/soc/intel/apollolake/pmutil.c</span><br><span>+++ b/src/soc/intel/apollolake/pmutil.c</span><br><span>@@ -28,11 +28,13 @@</span><br><span> #include <intelblocks/msr.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <intelblocks/rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <rules.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/cpu.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span> #include <timer.h></span><br><span> #include <security/vboot/vbnv.h></span><br><span> #include "chip.h"</span><br><span>@@ -133,15 +135,6 @@</span><br><span> return gpe_sts_bits;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t soc_reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t tco_en = inl(ACPI_BASE_ADDRESS + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- outl(tco_sts, ACPI_BASE_ADDRESS + TCO_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- return tco_sts & tco_en;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void soc_clear_pm_registers(uintptr_t pmc_bar)</span><br><span> {</span><br><span> uint32_t gen_pmcon1;</span><br><span>@@ -173,14 +166,18 @@</span><br><span> {</span><br><span> uintptr_t pmc_bar0 = read_pmc_mmio_bar();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco1_sts = tco_read_reg(TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco2_sts = tco_read_reg(TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> ps->prsts = read32((void *)(pmc_bar0 + PRSTS));</span><br><span> ps->gen_pmcon1 = read32((void *)(pmc_bar0 + GEN_PMCON1));</span><br><span> ps->gen_pmcon2 = read32((void *)(pmc_bar0 + GEN_PMCON2));</span><br><span> ps->gen_pmcon3 = read32((void *)(pmc_bar0 + GEN_PMCON3));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "prsts: %08x tco_sts: %08x\n",</span><br><span style="color: hsl(0, 100%, 40%);">- ps->prsts, ps->tco_sts);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "prsts: %08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->prsts);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "tco_sts: %04x %04x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco1_sts, ps->tco2_sts);</span><br><span> printk(BIOS_DEBUG,</span><br><span> "gen_pmcon1: %08x gen_pmcon2: %08x gen_pmcon3: %08x\n",</span><br><span> ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);</span><br><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 662f29d..92983ff 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -71,6 +71,8 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_SMM</span><br><span> select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP</span><br><span> select SOC_INTEL_COMMON_BLOCK_SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_TCO</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE</span><br><span> select SOC_INTEL_COMMON_BLOCK_TIMER</span><br><span> select SOC_INTEL_COMMON_BLOCK_UART</span><br><span> select SOC_INTEL_COMMON_BLOCK_XDCI</span><br><span>diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>index a2e6352..3eedd64 100644</span><br><span>--- a/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/cannonlake/bootblock/pch.c</span><br><span>@@ -23,6 +23,7 @@</span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <intelblocks/rtc.h></span><br><span> #include <intelblocks/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <soc/bootblock.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/lpc.h></span><br><span>@@ -45,8 +46,6 @@</span><br><span> #define PCR_DMI_ACPIBDID 0x27B8</span><br><span> #define PCR_DMI_PMBASEA 0x27AC</span><br><span> #define PCR_DMI_PMBASEC 0x27B0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_TCOBASE 0x2778</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */</span><br><span> </span><br><span> #define PCR_DMI_LPCIOD 0x2770</span><br><span> #define PCR_DMI_LPCIOE 0x2774</span><br><span>@@ -111,35 +110,6 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_config_tco(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcobase;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcocnt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable TCO in SMBUS Device first before changing Base Address */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~TCO_BASE_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program TCO Base */</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = TCO_BASE_ADDRESS;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, tcobase);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable TCO in SMBUS */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_BASE_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program TCO timer halt */</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt = inw(tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt |= TCO_TMR_HLT;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tcocnt, tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void pch_early_iorange_init(void)</span><br><span> {</span><br><span> uint16_t dec_rng, dec_en = 0;</span><br><span>@@ -171,7 +141,7 @@</span><br><span> soc_config_acpibase();</span><br><span> </span><br><span> /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */</span><br><span style="color: hsl(0, 100%, 40%);">- soc_config_tco();</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_enable_bar();</span><br><span> </span><br><span> /* Program SMBUS_BASE_ADDRESS and Enable it */</span><br><span> smbus_common_init();</span><br><span>diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c</span><br><span>index 5216460..2e8468a 100644</span><br><span>--- a/src/soc/intel/cannonlake/finalize.c</span><br><span>+++ b/src/soc/intel/cannonlake/finalize.c</span><br><span>@@ -23,6 +23,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <intelblocks/lpc_lib.h></span><br><span> #include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <reg_script.h></span><br><span> #include <spi-generic.h></span><br><span> #include <soc/p2sb.h></span><br><span>@@ -55,17 +56,11 @@</span><br><span> {</span><br><span> device_t dev;</span><br><span> uint32_t reg32;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcobase, tcocnt;</span><br><span> uint8_t *pmcbase;</span><br><span> config_t *config;</span><br><span> uint8_t reg8;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO Lock down */</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = smbus_tco_regs();</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt = inw(tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt |= TCO_LOCK;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tcocnt, tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_lockdown();</span><br><span> /*</span><br><span> * Disable ACPI PM timer based on dt policy</span><br><span> *</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h</span><br><span>index 9f1cf34..cf2eae8 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/smbus.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/smbus.h</span><br><span>@@ -33,6 +33,7 @@</span><br><span> #define TCO_TIMEOUT (1 << 3)</span><br><span> #define TCO2_STS 0x06</span><br><span> #define TCO2_STS_SECOND_TO (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO2_STS_BOOT (1 << 2)</span><br><span> #define TCO1_CNT 0x08</span><br><span> #define TCO_LOCK (1 << 12)</span><br><span> #define TCO_TMR_HLT (1 << 11)</span><br><span>diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c</span><br><span>index 4db4d63..df8ecdc 100644</span><br><span>--- a/src/soc/intel/cannonlake/pmutil.c</span><br><span>+++ b/src/soc/intel/cannonlake/pmutil.c</span><br><span>@@ -29,6 +29,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <intelblocks/rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <halt.h></span><br><span> #include <rules.h></span><br><span> #include <stdlib.h></span><br><span>@@ -154,38 +155,6 @@</span><br><span> return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uint16_t smbus_tco_regs(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return ALIGN_DOWN(reg16, 0x20);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t soc_reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tco1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tco2_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tcobase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = smbus_tco_regs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO Status 2 register */</span><br><span style="color: hsl(0, 100%, 40%);">- tco2_sts = inw(tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- tco2_sts |= TCO2_STS_SECOND_TO;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tco2_sts, tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO Status 1 register */</span><br><span style="color: hsl(0, 100%, 40%);">- tco1_sts = inw(tcobase + TCO1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear SECOND_TO_STS bit */</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco2_sts & TCO2_STS_SECOND_TO)</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return (tco2_sts << 16) | tco1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> uintptr_t soc_read_pmc_base(void)</span><br><span> {</span><br><span> return (uintptr_t)pmc_mmio_regs();</span><br><span>diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c</span><br><span>index b62e5fd..1df60e0 100644</span><br><span>--- a/src/soc/intel/cannonlake/romstage/power_state.c</span><br><span>+++ b/src/soc/intel/cannonlake/romstage/power_state.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/device.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <string.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span>@@ -75,13 +76,10 @@</span><br><span> </span><br><span> void soc_fill_power_state(struct chipset_power_state *ps)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcobase;</span><br><span> uint8_t *pmc;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = smbus_tco_regs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- ps->tco1_sts = inw(tcobase + TCO1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- ps->tco2_sts = inw(tcobase + TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco1_sts = tco_read_reg(TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco2_sts = tco_read_reg(TCO2_STS);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",</span><br><span> ps->tco1_sts, ps->tco2_sts);</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>index d631f01..87feb05 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h</span><br><span>@@ -93,13 +93,6 @@</span><br><span> */</span><br><span> const char * const *soc_tco_sts_array(size_t *a);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * Resets the tco status registers. This function clears the tco_sts register</span><br><span style="color: hsl(0, 100%, 40%);">- * and returns the sts and enable bits set.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t soc_reset_tco_status(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* GPE */</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/tco.h b/src/soc/intel/common/block/include/intelblocks/tco.h</span><br><span>new file mode 100644</span><br><span>index 0000000..7d4683c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/tco.h</span><br><span>@@ -0,0 +1,33 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_INTEL_COMMON_BLOCK_TCO_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_INTEL_COMMON_BLOCK_TCO_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Stop TCO timer */</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_timer_disable(void);</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable TCO BAR using SMBUS TCO base to access TCO related register */</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_enable_bar(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_lockdown(void);</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Resets the tco status registers. This function clears the tco_sts register</span><br><span style="color: hsl(120, 100%, 40%);">+ * and returns the sts and enable bits set.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t tco_reset_status(void);</span><br><span style="color: hsl(120, 100%, 40%);">+uint16_t tco_read_reg(uint16_t tco_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_write_reg(uint16_t tco_reg, uint16_t value);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* SOC_INTEL_COMMON_BLOCK_TCO_H */</span><br><span>diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>index 38d4196..246dab1 100644</span><br><span>--- a/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>+++ b/src/soc/intel/common/block/pmc/pmclib.c</span><br><span>@@ -21,6 +21,7 @@</span><br><span> #include <halt.h></span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <intelblocks/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <soc/pm.h></span><br><span> #include <string.h></span><br><span> #include <timer.h></span><br><span>@@ -249,7 +250,7 @@</span><br><span> </span><br><span> uint32_t pmc_clear_tco_status(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return print_tco_status(soc_reset_tco_status());</span><br><span style="color: hsl(120, 100%, 40%);">+ return print_tco_status(tco_reset_status());</span><br><span> }</span><br><span> </span><br><span> /* GPE */</span><br><span>diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig</span><br><span>index 4514383..1d22998 100644</span><br><span>--- a/src/soc/intel/common/block/smbus/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/smbus/Kconfig</span><br><span>@@ -2,3 +2,14 @@</span><br><span> bool</span><br><span> help</span><br><span> Intel Processor common SMBus support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_TCO</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel Processor common TCO support</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_TCO_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ depends on SOC_INTEL_COMMON_BLOCK_TCO</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Select this config to enable TCO BAR through SMBUS</span><br><span>diff --git a/src/soc/intel/common/block/smbus/Makefile.inc b/src/soc/intel/common/block/smbus/Makefile.inc</span><br><span>index 1a10fd9..309ad9a 100644</span><br><span>--- a/src/soc/intel/common/block/smbus/Makefile.inc</span><br><span>+++ b/src/soc/intel/common/block/smbus/Makefile.inc</span><br><span>@@ -1,8 +1,15 @@</span><br><span> bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c</span><br><span> bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c</span><br><span> romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c</span><br><span> </span><br><span> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c</span><br><span> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c</span><br><span>diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c</span><br><span>new file mode 100644</span><br><span>index 0000000..02783a0</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/block/smbus/tco.c</span><br><span>@@ -0,0 +1,128 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_TCOBASE 0x2778</span><br><span style="color: hsl(120, 100%, 40%);">+/* Enable TCO I/O range decode. */</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCOEN (1 << 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Get base address of TCO I/O registers. */</span><br><span style="color: hsl(120, 100%, 40%);">+static uint16_t tco_get_bar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return TCO_BASE_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint16_t tco_read_reg(uint16_t tco_reg)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcobase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = tco_get_bar();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return inw(tcobase + tco_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_write_reg(uint16_t tco_reg, uint16_t value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcobase;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = tco_get_bar();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ outw(value, tcobase + tco_reg);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_lockdown(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcocnt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO Lock down */</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt = tco_read_reg(TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt |= TCO_LOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_write_reg(TCO1_CNT, tcocnt);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uint32_t tco_reset_status(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tco1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tco2_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO Status 2 register */</span><br><span style="color: hsl(120, 100%, 40%);">+ tco2_sts = tco_read_reg(TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_write_reg(TCO2_STS, tco2_sts);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TCO Status 1 register */</span><br><span style="color: hsl(120, 100%, 40%);">+ tco1_sts = tco_read_reg(TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear SECOND_TO_STS bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (tco2_sts & TCO2_STS_SECOND_TO)</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_write_reg(TCO2_STS, tco2_sts & ~TCO2_STS_SECOND_TO);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return (tco2_sts << 16) | tco1_sts;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_timer_disable(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcocnt;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program TCO timer halt */</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt = tco_read_reg(TCO1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ tcocnt |= TCO_TMR_HLT;</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_write_reg(TCO1_CNT, tcocnt);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE)</span><br><span style="color: hsl(120, 100%, 40%);">+void tco_enable_bar(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t tcobase;</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ int devfn = PCH_DEVFN_SMBUS;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = PCH_DEV_SMBUS;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable TCO in SMBUS Device first before changing Base Address */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(dev, TCOCTL);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~TCO_BASE_EN;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, TCOCTL, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Program TCO Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ tcobase = tco_get_bar();</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, TCOBASE, tcobase);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable TCO in SMBUS */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_timer_disable();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>index 8ed7239..cdd26da 100644</span><br><span>--- a/src/soc/intel/common/block/smm/smihandler.c</span><br><span>+++ b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>@@ -31,6 +31,7 @@</span><br><span> #include <soc/pm.h></span><br><span> #include <soc/gpio.h></span><br><span> #include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/smbus.h></span><br><span> #include <spi-generic.h></span><br><span> #include <stdint.h></span><br><span> #include <stdlib.h></span><br><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index 5fbd57b..a42f87c 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -86,6 +86,8 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP</span><br><span> select SOC_INTEL_COMMON_BLOCK_SPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_TIMER</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_TCO</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE</span><br><span> select SOC_INTEL_COMMON_BLOCK_UART</span><br><span> select SOC_INTEL_COMMON_BLOCK_VMX</span><br><span> select SOC_INTEL_COMMON_BLOCK_XDCI</span><br><span>diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>index 0856ee2..1b5b8b4 100644</span><br><span>--- a/src/soc/intel/skylake/bootblock/pch.c</span><br><span>+++ b/src/soc/intel/skylake/bootblock/pch.c</span><br><span>@@ -27,6 +27,7 @@</span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <intelblocks/rtc.h></span><br><span> #include <intelblocks/smbus.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <soc/bootblock.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/p2sb.h></span><br><span>@@ -43,7 +44,6 @@</span><br><span> #define PCR_DMI_ACPIBDID 0x27B8</span><br><span> #define PCR_DMI_PMBASEA 0x27AC</span><br><span> #define PCR_DMI_PMBASEC 0x27B0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_TCOBASE 0x2778</span><br><span> </span><br><span> void bootblock_pch_early_init(void)</span><br><span> {</span><br><span>@@ -111,37 +111,6 @@</span><br><span> pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void soc_config_tco(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32 = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcobase;</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcocnt;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Disable TCO in SMBUS Device first before changing Base Address */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 &= ~TCO_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program TCO Base */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Enable TCO in SMBUS */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1]</span><br><span style="color: hsl(0, 100%, 40%);">- * to [SMBUS PCI offset 50h[15:5], 1].</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_write32(PID_DMI, PCR_DMI_TCOBASE, TCO_BASE_ADDDRESS | (1 << 1));</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Program TCO timer halt */</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase &= ~0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt = inw(tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- tcocnt |= TCO_TMR_HLT;</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tcocnt, tcobase + TCO1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static int pch_check_decode_enable(void)</span><br><span> {</span><br><span> uint32_t dmi_control;</span><br><span>@@ -195,7 +164,7 @@</span><br><span> soc_config_pwrmbase();</span><br><span> </span><br><span> /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */</span><br><span style="color: hsl(0, 100%, 40%);">- soc_config_tco();</span><br><span style="color: hsl(120, 100%, 40%);">+ tco_enable_bar();</span><br><span> </span><br><span> /* Program SMBUS_BASE_ADDRESS and Enable it */</span><br><span> smbus_common_init();</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h</span><br><span>index f2fde71..475d79d 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/iomap.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/iomap.h</span><br><span>@@ -87,7 +87,7 @@</span><br><span> #define ACPI_BASE_ADDRESS 0x1800</span><br><span> #define ACPI_BASE_SIZE 0x100</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define TCO_BASE_ADDDRESS 0x400</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_ADDRESS 0x400</span><br><span> #define TCO_BASE_SIZE 0x20</span><br><span> </span><br><span> #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h</span><br><span>index 11585a1..5902e82 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/pm.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/pm.h</span><br><span>@@ -184,9 +184,6 @@</span><br><span> /* Get base address PMC memory mapped registers. */</span><br><span> uint8_t *pmc_mmio_regs(void);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* Get base address of TCO I/O registers. */</span><br><span style="color: hsl(0, 100%, 40%);">-uint16_t smbus_tco_regs(void);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* Set the DISB after DRAM init */</span><br><span> void pmc_set_disb(void);</span><br><span> </span><br><span>diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h</span><br><span>index aeaf1d9..d725269 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/smbus.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/smbus.h</span><br><span>@@ -25,7 +25,7 @@</span><br><span> /* SMBUS TCO base address. */</span><br><span> #define TCOBASE 0x50</span><br><span> #define TCOCTL 0x54</span><br><span style="color: hsl(0, 100%, 40%);">-#define TCO_EN (1 << 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define TCO_BASE_EN (1 << 8)</span><br><span> </span><br><span> /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */</span><br><span> #define TCO1_STS 0x04</span><br><span>diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c</span><br><span>index d05c812..22e2990 100644</span><br><span>--- a/src/soc/intel/skylake/pmutil.c</span><br><span>+++ b/src/soc/intel/skylake/pmutil.c</span><br><span>@@ -30,6 +30,7 @@</span><br><span> #include <intelblocks/pmclib.h></span><br><span> #include <halt.h></span><br><span> #include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/tco.h></span><br><span> #include <rules.h></span><br><span> #include <stdlib.h></span><br><span> #include <soc/gpe.h></span><br><span>@@ -170,40 +171,6 @@</span><br><span> return (void *)(uintptr_t) reg32;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-uint16_t smbus_tco_regs(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 &= ~0x1f;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return reg16;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t soc_reset_tco_status(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tco1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tco2_sts;</span><br><span style="color: hsl(0, 100%, 40%);">- u16 tcobase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = smbus_tco_regs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO Status 2 register */</span><br><span style="color: hsl(0, 100%, 40%);">- tco2_sts = inw(tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tco2_sts, tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* TCO Status 1 register */</span><br><span style="color: hsl(0, 100%, 40%);">- tco1_sts = inw(tcobase + TCO1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear SECOND_TO_STS bit */</span><br><span style="color: hsl(0, 100%, 40%);">- if (tco2_sts & TCO2_STS_SECOND_TO)</span><br><span style="color: hsl(0, 100%, 40%);">- outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return (tco2_sts << 16) | tco1_sts;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> uintptr_t soc_read_pmc_base(void)</span><br><span> {</span><br><span> return (uintptr_t) (pmc_mmio_regs());</span><br><span>@@ -283,13 +250,10 @@</span><br><span> </span><br><span> void soc_fill_power_state(struct chipset_power_state *ps)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t tcobase;</span><br><span> uint8_t *pmc;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- tcobase = smbus_tco_regs();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- ps->tco1_sts = inw(tcobase + TCO1_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- ps->tco2_sts = inw(tcobase + TCO2_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco1_sts = tco_read_reg(TCO1_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ ps->tco2_sts = tco_read_reg(TCO2_STS);</span><br><span> </span><br><span> printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",</span><br><span> ps->tco1_sts, ps->tco2_sts);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26166">change 26166</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 </div>
<div style="display:none"> Gerrit-Change-Number: 26166 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>