[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Move common uart function to block/uart
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Tue May 8 10:55:31 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26164
Change subject: soc/intel/common/block: Move common uart function to block/uart
......................................................................
soc/intel/common/block: Move common uart function to block/uart
This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.
BUG=none
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.
Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/apollolake/include/soc/iomap.h
M src/soc/intel/apollolake/uart.c
M src/soc/intel/cannonlake/uart.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/skylake/uart.c
5 files changed, 42 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/26164/1
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 9a2500c..dc0b18e 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -54,4 +54,12 @@
#define EARLY_I2C_BASE_ADDRESS 0xfe020000
#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
+#define UART_DEBUG_BASE_0_SIZE 0x1000
+/*
+ * We provide base address of UART port we use in Kconfig directly.
+ * Use that base address irrespective of port id since address will be correct
+ * for selected port by user.
+ */
+#define UART_BASE_0_ADDR(x) CONFIG_CONSOLE_UART_BASE_ADDRESS
+
#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
index 54b280d..c6acd97 100644
--- a/src/soc/intel/apollolake/uart.c
+++ b/src/soc/intel/apollolake/uart.c
@@ -20,13 +20,11 @@
* shouldn't cause any fragmentation.
*/
-#include <cbmem.h>
#include <console/uart.h>
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/uart.h>
#include <soc/gpio.h>
-#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/uart.h>
@@ -76,35 +74,6 @@
}
-#if !ENV_SMM
-void pch_uart_read_resources(struct device *dev)
-{
- pci_dev_read_resources(dev);
-
- if (IS_ENABLED(CONFIG_SOC_UART_DEBUG) &&
- uart_is_debug_controller(dev)) {
- /* will override existing resource. */
- fixed_mem_resource(dev, PCI_BASE_ADDRESS_0,
- CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0);
- }
-}
-#endif
-
-bool pch_uart_init_debug_controller_on_resume(void)
-{
- global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
- if (gnvs)
- return !!gnvs->uior;
-
- return false;
-}
-
-device_t pch_uart_get_debug_controller(void)
-{
- return _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE);
-}
-
uintptr_t uart_platform_base(int idx)
{
return CONFIG_CONSOLE_UART_BASE_ADDRESS;
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 6aad685..5ccad3f 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -14,16 +14,13 @@
*/
#include <assert.h>
-#include <cbmem.h>
#include <console/uart.h>
-#include <device/pci.h>
#include <device/pci_def.h>
#include <intelblocks/gpio.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/uart.h>
#include <soc/iomap.h>
-#include <soc/nvs.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@@ -85,41 +82,3 @@
return UART_BASE_0_ADDR(idx);
}
#endif
-
-device_t pch_uart_get_debug_controller(void)
-{
- switch (CONFIG_UART_FOR_CONSOLE) {
- case 0:
- return PCH_DEV_UART0;
- case 1:
- return PCH_DEV_UART1;
- case 2:
- default:
- return PCH_DEV_UART2;
- }
-}
-
-void pch_uart_read_resources(struct device *dev)
-{
- pci_dev_read_resources(dev);
-
- /* Set the configured UART base address for the debug port */
- if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
- struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
- /* Need to set the base and size for the resource allocator. */
- res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
- res->size = UART_DEBUG_BASE_0_SIZE;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
- IORESOURCE_FIXED;
- }
-}
-
-bool pch_uart_init_debug_controller_on_resume(void)
-{
- global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
- if (gnvs)
- return !!gnvs->uior;
-
- return false;
-}
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index cdbe56b..8914da4 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <compiler.h>
+#include <cbmem.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
@@ -22,6 +23,9 @@
#include <device/pci_ops.h>
#include <intelblocks/lpss.h>
#include <intelblocks/uart.h>
+#include <soc/pci_devs.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
@@ -46,15 +50,17 @@
uart_lpss_init(baseaddr);
}
-__weak device_t pch_uart_get_debug_controller(void)
+device_t pch_uart_get_debug_controller(void)
{
- /*
- * device_t can either be a pointer to struct device (e.g. ramstage) or
- * a simple integer (e.g. SMM) depending upon whether __SIMPLE_DEVICE__
- * is defined for the stage. Thus, the return requires additional
- * casting to uintptr_t.
- */
- return (device_t)(uintptr_t)NULL;
+ switch (CONFIG_UART_FOR_CONSOLE) {
+ case 0:
+ return PCH_DEV_UART0;
+ case 1:
+ return PCH_DEV_UART1;
+ case 2:
+ default:
+ return PCH_DEV_UART2;
+ }
}
bool uart_debug_controller_is_initialized(void)
@@ -79,14 +85,28 @@
#if ENV_RAMSTAGE
-__weak void pch_uart_read_resources(struct device *dev)
+void pch_uart_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
+
+ /* Set the configured UART base address for the debug port */
+ if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
+ struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ /* Need to set the base and size for the resource allocator. */
+ res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
+ res->size = UART_DEBUG_BASE_0_SIZE;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+ IORESOURCE_FIXED;
+ }
}
-__weak bool pch_uart_init_debug_controller_on_resume(void)
+bool pch_uart_init_debug_controller_on_resume(void)
{
- /* By default, do not initialize controller. */
+ global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+ if (gnvs)
+ return !!gnvs->uior;
+
return false;
}
@@ -173,8 +193,8 @@
};
static const struct pci_driver pch_uart __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pci_device_ids,
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
};
#endif /* ENV_RAMSTAGE */
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 6f3c21e..69b0e95 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -14,16 +14,13 @@
* GNU General Public License for more details.
*/
-#include <cbmem.h>
#include <console/uart.h>
-#include <device/pci.h>
#include <device/pci_def.h>
#include <gpio.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/uart.h>
#include <soc/bootblock.h>
-#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@@ -66,35 +63,3 @@
gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
-
-#if !ENV_SMM
-void pch_uart_read_resources(struct device *dev)
-{
- pci_dev_read_resources(dev);
-
- /* Set the configured UART base address for the debug port */
- if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {
- struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
- /* Need to set the base and size for the resource allocator. */
- res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
- res->size = UART_DEBUG_BASE_0_SIZE;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
- IORESOURCE_FIXED;
- }
-}
-#endif
-
-bool pch_uart_init_debug_controller_on_resume(void)
-{
- global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
- if (gnvs)
- return !!gnvs->uior;
-
- return false;
-}
-
-device_t pch_uart_get_debug_controller(void)
-{
- return PCH_DEV_UART2;
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Gerrit-Change-Number: 26164
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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