[coreboot-gerrit] Change in coreboot[master]: vc/amd/00670F00: Sync AGESA.h with PI blob

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/26145


Change subject: vc/amd/00670F00: Sync AGESA.h with PI blob
......................................................................

vc/amd/00670F00: Sync AGESA.h with PI blob

Add a new callout definition for AgesaGetHeapBaseInDram and displace
AgesaHeapRebase (which was merged too soon) in the ordering.  Also
add its structure.

AGESA will be modified to ask coreboot for the location for temporary
storage of heap data at the end of InitPost.  The old methodology is
to use 0xb0000 but the change will allow coreboot to determine the
location.

BUG=b:74518368

Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/vendorcode/amd/pi/00670F00/AGESA.h
1 file changed, 17 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/26145/1

diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h
index ba1e505..4c30bbe 100644
--- a/src/vendorcode/amd/pi/00670F00/AGESA.h
+++ b/src/vendorcode/amd/pi/00670F00/AGESA.h
@@ -68,7 +68,8 @@
 #define AGESA_IDLE_AN_AP                        0x00028107ul
 #define AGESA_WAIT_FOR_ALL_APS                  0x00028108ul
 #define AGESA_HALT_THIS_AP                      0x00028109ul
-#define AGESA_HEAP_REBASE                       0x0002810aul
+#define AGESA_GET_HEAP_BASE_IN_DRAM             0x0002810Aul
+#define AGESA_HEAP_REBASE                       0x0002810Bul
 
 // AGESA ADVANCED CALLOUTS, Memory
 #define AGESA_READ_SPD                 0x00028140ul
@@ -2528,6 +2529,15 @@
                                            ///  be enabled
 } AGESA_HALT_THIS_AP_PARAMS;
 
+/// Parameters structure for interface call-out AgesaGetHeapBaseInDram
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration
+                                                ///  header
+     OUT    UINTN             HeapDramAddress;  ///< The main memory address
+                                                ///  where heap contents will be
+                                                ///  temporarily stored
+} AGESA_HEAP_BASE_IN_DRAM_PARAMS;
+
 /// VoltageType values
 typedef enum {
   VTYPE_CPU_VREF,                                    ///< Cpu side Vref
@@ -2615,6 +2625,12 @@
   );
 
 AGESA_STATUS
+AgesaGetHeapBaseInDram (
+  IN       UINTN                            FcnData,
+  IN OUT   AGESA_HEAP_BASE_IN_DRAM_PARAMS   *HeapBaseInDramParams
+  );
+
+AGESA_STATUS
 AgesaRunFcnOnAp (
   IN        UINTN               ApicIdOfCore,
   IN        AP_EXE_PARAMS       *LaunchApParams

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be
Gerrit-Change-Number: 26145
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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