[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Move smihandler common functions into block/s...
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon May 7 17:48:15 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26138
Change subject: soc/intel/common/block: Move smihandler common functions into block/smihandler
......................................................................
soc/intel/common/block: Move smihandler common functions into block/smihandler
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/smihandler.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/apollolake/smihandler.c
M src/soc/intel/cannonlake/include/soc/pm.h
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/smihandler.c
7 files changed, 31 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/26138/1
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c
index 5b28db2..fdab118 100644
--- a/src/soc/intel/apollolake/smihandler.c
+++ b/src/soc/intel/apollolake/smihandler.c
@@ -34,16 +34,6 @@
return &em64t100_smm_ops;
}
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_SMI_STS) |
- SMI_HANDLER_SCI_EN(SLP_SMI_STS);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[32] = {
[SLP_SMI_STS] = smihandler_southbridge_sleep,
[APM_SMI_STS] = smihandler_southbridge_apmc,
diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h
index 1494d56..f1fb54f 100644
--- a/src/soc/intel/cannonlake/include/soc/pm.h
+++ b/src/soc/intel/cannonlake/include/soc/pm.h
@@ -75,8 +75,8 @@
#define GPE0_STS_BIT 9
#define PM1_STS_BIT 8
#define SWSMI_TMR_STS_BIT 6
-#define APM_STS_BIT 5
-#define SMI_ON_SLP_EN_STS_BIT 4
+#define APM_SMI_STS 5
+#define SLP_SMI_STS 4
#define LEGACY_USB_STS_BIT 3
#define BIOS_STS_BIT 2
#define GPE_CNTL 0x42
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 951d886..4db4d63 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -52,8 +52,8 @@
static const char *const smi_sts_bits[] = {
[BIOS_STS_BIT] = "BIOS",
[LEGACY_USB_STS_BIT] = "LEGACY_USB",
- [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",
- [APM_STS_BIT] = "APM",
+ [SLP_SMI_STS] = "SLP_SMI",
+ [APM_SMI_STS] = "APM",
[SWSMI_TMR_STS_BIT] = "SWSMI_TMR",
[PM1_STS_BIT] = "PM1",
[GPE0_STS_BIT] = "GPE0",
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 1774bc3..0a2536c 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -18,10 +18,8 @@
#include <chip.h>
#include <console/console.h>
#include <device/pci_def.h>
-#include <intelblocks/fast_spi.h>
#include <intelblocks/cse.h>
#include <intelblocks/smihandler.h>
-#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -54,39 +52,9 @@
pch_disable_heci();
}
-void smihandler_soc_check_illegal_access(uint32_t tco_sts)
-{
- if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)
- && fast_spi_wpd_status()))
- return;
-
- /*
- * BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
- *
- * This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
- */
- printk(BIOS_DEBUG, "Switching back to RO\n");
- fast_spi_enable_wp();
-}
-
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
- [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
- [APM_STS_BIT] = smihandler_southbridge_apmc,
+ [SLP_SMI_STS] = smihandler_southbridge_sleep,
+ [APM_SMI_STS] = smihandler_southbridge_apmc,
[PM1_STS_BIT] = smihandler_southbridge_pm1,
[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
[GPIO_STS_BIT] = smihandler_southbridge_gpi,
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index d8ac2f3..8ed7239 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -54,7 +54,11 @@
/* SMI handlers that should be serviced in SCI mode too. */
__weak uint32_t smihandler_soc_get_sci_mask(void)
{
- return 0; /* No valid SCI mask for SMI handler */
+ uint32_t sci_mask =
+ SMI_HANDLER_SCI_EN(APM_SMI_STS) |
+ SMI_HANDLER_SCI_EN(SLP_SMI_STS);
+
+ return sci_mask;
}
/*
@@ -64,7 +68,22 @@
__weak void smihandler_soc_check_illegal_access(
uint32_t tco_sts)
{
- return;
+ if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+ && fast_spi_wpd_status()))
+ return;
+
+ /*
+ * BWE is RW, so the SMI was caused by a
+ * write to BWE, not by a write to the BIOS
+ *
+ * This is the place where we notice someone
+ * is trying to tinker with the BIOS. We are
+ * trying to be nice and just ignore it. A more
+ * resolute answer would be to power down the
+ * box.
+ */
+ printk(BIOS_DEBUG, "Switching back to RO\n");
+ fast_spi_enable_wp();
}
/* Mainboard overrides. */
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index b7d6446..11585a1 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -86,8 +86,8 @@
#define GPE0_STS_BIT 9
#define PM1_STS_BIT 8
#define SWSMI_TMR_STS_BIT 6
-#define APM_STS_BIT 5
-#define SMI_ON_SLP_EN_STS_BIT 4
+#define APM_SMI_STS 5
+#define SLP_SMI_STS 4
#define LEGACY_USB_STS_BIT 3
#define BIOS_STS_BIT 2
#define UPWRC 0x3c
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index e402ba5..786e135 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -25,39 +25,9 @@
return &em64t101_smm_ops;
}
-void smihandler_soc_check_illegal_access(uint32_t tco_sts)
-{
- if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)
- && fast_spi_wpd_status()))
- return;
-
- /*
- * BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
- *
- * This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
- */
- printk(BIOS_DEBUG, "Switching back to RO\n");
- fast_spi_enable_wp();
-}
-
-/* SMI handlers that should be serviced in SCI mode too. */
-uint32_t smihandler_soc_get_sci_mask(void)
-{
- uint32_t sci_mask =
- SMI_HANDLER_SCI_EN(APM_STS_BIT) |
- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);
-
- return sci_mask;
-}
-
const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
- [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
- [APM_STS_BIT] = smihandler_southbridge_apmc,
+ [SLP_SMI_STS] = smihandler_southbridge_sleep,
+ [APM_SMI_STS] = smihandler_southbridge_apmc,
[PM1_STS_BIT] = smihandler_southbridge_pm1,
[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
[GPIO_STS_BIT] = smihandler_southbridge_gpi,
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03
Gerrit-Change-Number: 26138
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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