<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26138">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Move smihandler common functions into block/smihandler<br><br>This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving<br>common soc code into common/block/smihandler.<br><br>BUG=b:78109109<br>BRANCH=none<br>TEST=Build and boot KBL/CNL/APL platform.<br><br>Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/apollolake/smihandler.c<br>M src/soc/intel/cannonlake/include/soc/pm.h<br>M src/soc/intel/cannonlake/pmutil.c<br>M src/soc/intel/cannonlake/smihandler.c<br>M src/soc/intel/common/block/smm/smihandler.c<br>M src/soc/intel/skylake/include/soc/pm.h<br>M src/soc/intel/skylake/smihandler.c<br>7 files changed, 31 insertions(+), 84 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/26138/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c</span><br><span>index 5b28db2..fdab118 100644</span><br><span>--- a/src/soc/intel/apollolake/smihandler.c</span><br><span>+++ b/src/soc/intel/apollolake/smihandler.c</span><br><span>@@ -34,16 +34,6 @@</span><br><span> return &em64t100_smm_ops;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* SMI handlers that should be serviced in SCI mode too. */</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t smihandler_soc_get_sci_mask(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t sci_mask =</span><br><span style="color: hsl(0, 100%, 40%);">- SMI_HANDLER_SCI_EN(APM_SMI_STS) |</span><br><span style="color: hsl(0, 100%, 40%);">- SMI_HANDLER_SCI_EN(SLP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return sci_mask;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> const smi_handler_t southbridge_smi[32] = {</span><br><span> [SLP_SMI_STS] = smihandler_southbridge_sleep,</span><br><span> [APM_SMI_STS] = smihandler_southbridge_apmc,</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h</span><br><span>index 1494d56..f1fb54f 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pm.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pm.h</span><br><span>@@ -75,8 +75,8 @@</span><br><span> #define GPE0_STS_BIT 9</span><br><span> #define PM1_STS_BIT 8</span><br><span> #define SWSMI_TMR_STS_BIT 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define APM_STS_BIT 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMI_ON_SLP_EN_STS_BIT 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define APM_SMI_STS 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_SMI_STS 4</span><br><span> #define LEGACY_USB_STS_BIT 3</span><br><span> #define BIOS_STS_BIT 2</span><br><span> #define GPE_CNTL 0x42</span><br><span>diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c</span><br><span>index 951d886..4db4d63 100644</span><br><span>--- a/src/soc/intel/cannonlake/pmutil.c</span><br><span>+++ b/src/soc/intel/cannonlake/pmutil.c</span><br><span>@@ -52,8 +52,8 @@</span><br><span> static const char *const smi_sts_bits[] = {</span><br><span> [BIOS_STS_BIT] = "BIOS",</span><br><span> [LEGACY_USB_STS_BIT] = "LEGACY_USB",</span><br><span style="color: hsl(0, 100%, 40%);">- [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI",</span><br><span style="color: hsl(0, 100%, 40%);">- [APM_STS_BIT] = "APM",</span><br><span style="color: hsl(120, 100%, 40%);">+ [SLP_SMI_STS] = "SLP_SMI",</span><br><span style="color: hsl(120, 100%, 40%);">+ [APM_SMI_STS] = "APM",</span><br><span> [SWSMI_TMR_STS_BIT] = "SWSMI_TMR",</span><br><span> [PM1_STS_BIT] = "PM1",</span><br><span> [GPE0_STS_BIT] = "GPE0",</span><br><span>diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c</span><br><span>index 1774bc3..0a2536c 100644</span><br><span>--- a/src/soc/intel/cannonlake/smihandler.c</span><br><span>+++ b/src/soc/intel/cannonlake/smihandler.c</span><br><span>@@ -18,10 +18,8 @@</span><br><span> #include <chip.h></span><br><span> #include <console/console.h></span><br><span> #include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/fast_spi.h></span><br><span> #include <intelblocks/cse.h></span><br><span> #include <intelblocks/smihandler.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/p2sb.h></span><br><span> #include <soc/pci_devs.h></span><br><span> #include <soc/pm.h></span><br><span> </span><br><span>@@ -54,39 +52,9 @@</span><br><span> pch_disable_heci();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void smihandler_soc_check_illegal_access(uint32_t tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)</span><br><span style="color: hsl(0, 100%, 40%);">- && fast_spi_wpd_status()))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * BWE is RW, so the SMI was caused by a</span><br><span style="color: hsl(0, 100%, 40%);">- * write to BWE, not by a write to the BIOS</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This is the place where we notice someone</span><br><span style="color: hsl(0, 100%, 40%);">- * is trying to tinker with the BIOS. We are</span><br><span style="color: hsl(0, 100%, 40%);">- * trying to be nice and just ignore it. A more</span><br><span style="color: hsl(0, 100%, 40%);">- * resolute answer would be to power down the</span><br><span style="color: hsl(0, 100%, 40%);">- * box.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Switching back to RO\n");</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_enable_wp();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMI handlers that should be serviced in SCI mode too. */</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t smihandler_soc_get_sci_mask(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t sci_mask =</span><br><span style="color: hsl(0, 100%, 40%);">- SMI_HANDLER_SCI_EN(APM_STS_BIT) |</span><br><span style="color: hsl(0, 100%, 40%);">- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return sci_mask;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> const smi_handler_t southbridge_smi[SMI_STS_BITS] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,</span><br><span style="color: hsl(0, 100%, 40%);">- [APM_STS_BIT] = smihandler_southbridge_apmc,</span><br><span style="color: hsl(120, 100%, 40%);">+ [SLP_SMI_STS] = smihandler_southbridge_sleep,</span><br><span style="color: hsl(120, 100%, 40%);">+ [APM_SMI_STS] = smihandler_southbridge_apmc,</span><br><span> [PM1_STS_BIT] = smihandler_southbridge_pm1,</span><br><span> [GPE0_STS_BIT] = smihandler_southbridge_gpe0,</span><br><span> [GPIO_STS_BIT] = smihandler_southbridge_gpi,</span><br><span>diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>index d8ac2f3..8ed7239 100644</span><br><span>--- a/src/soc/intel/common/block/smm/smihandler.c</span><br><span>+++ b/src/soc/intel/common/block/smm/smihandler.c</span><br><span>@@ -54,7 +54,11 @@</span><br><span> /* SMI handlers that should be serviced in SCI mode too. */</span><br><span> __weak uint32_t smihandler_soc_get_sci_mask(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return 0; /* No valid SCI mask for SMI handler */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t sci_mask =</span><br><span style="color: hsl(120, 100%, 40%);">+ SMI_HANDLER_SCI_EN(APM_SMI_STS) |</span><br><span style="color: hsl(120, 100%, 40%);">+ SMI_HANDLER_SCI_EN(SLP_SMI_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return sci_mask;</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>@@ -64,7 +68,22 @@</span><br><span> __weak void smihandler_soc_check_illegal_access(</span><br><span> uint32_t tco_sts)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)</span><br><span style="color: hsl(120, 100%, 40%);">+ && fast_spi_wpd_status()))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * BWE is RW, so the SMI was caused by a</span><br><span style="color: hsl(120, 100%, 40%);">+ * write to BWE, not by a write to the BIOS</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This is the place where we notice someone</span><br><span style="color: hsl(120, 100%, 40%);">+ * is trying to tinker with the BIOS. We are</span><br><span style="color: hsl(120, 100%, 40%);">+ * trying to be nice and just ignore it. A more</span><br><span style="color: hsl(120, 100%, 40%);">+ * resolute answer would be to power down the</span><br><span style="color: hsl(120, 100%, 40%);">+ * box.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Switching back to RO\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_enable_wp();</span><br><span> }</span><br><span> </span><br><span> /* Mainboard overrides. */</span><br><span>diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h</span><br><span>index b7d6446..11585a1 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/pm.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/pm.h</span><br><span>@@ -86,8 +86,8 @@</span><br><span> #define GPE0_STS_BIT 9</span><br><span> #define PM1_STS_BIT 8</span><br><span> #define SWSMI_TMR_STS_BIT 6</span><br><span style="color: hsl(0, 100%, 40%);">-#define APM_STS_BIT 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMI_ON_SLP_EN_STS_BIT 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define APM_SMI_STS 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define SLP_SMI_STS 4</span><br><span> #define LEGACY_USB_STS_BIT 3</span><br><span> #define BIOS_STS_BIT 2</span><br><span> #define UPWRC 0x3c</span><br><span>diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c</span><br><span>index e402ba5..786e135 100644</span><br><span>--- a/src/soc/intel/skylake/smihandler.c</span><br><span>+++ b/src/soc/intel/skylake/smihandler.c</span><br><span>@@ -25,39 +25,9 @@</span><br><span> return &em64t101_smm_ops;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void smihandler_soc_check_illegal_access(uint32_t tco_sts)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- if (!((tco_sts & (1 << 8)) && IS_ENABLED(CONFIG_SPI_FLASH_SMM)</span><br><span style="color: hsl(0, 100%, 40%);">- && fast_spi_wpd_status()))</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * BWE is RW, so the SMI was caused by a</span><br><span style="color: hsl(0, 100%, 40%);">- * write to BWE, not by a write to the BIOS</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This is the place where we notice someone</span><br><span style="color: hsl(0, 100%, 40%);">- * is trying to tinker with the BIOS. We are</span><br><span style="color: hsl(0, 100%, 40%);">- * trying to be nice and just ignore it. A more</span><br><span style="color: hsl(0, 100%, 40%);">- * resolute answer would be to power down the</span><br><span style="color: hsl(0, 100%, 40%);">- * box.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_DEBUG, "Switching back to RO\n");</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_enable_wp();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-/* SMI handlers that should be serviced in SCI mode too. */</span><br><span style="color: hsl(0, 100%, 40%);">-uint32_t smihandler_soc_get_sci_mask(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t sci_mask =</span><br><span style="color: hsl(0, 100%, 40%);">- SMI_HANDLER_SCI_EN(APM_STS_BIT) |</span><br><span style="color: hsl(0, 100%, 40%);">- SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return sci_mask;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> const smi_handler_t southbridge_smi[SMI_STS_BITS] = {</span><br><span style="color: hsl(0, 100%, 40%);">- [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,</span><br><span style="color: hsl(0, 100%, 40%);">- [APM_STS_BIT] = smihandler_southbridge_apmc,</span><br><span style="color: hsl(120, 100%, 40%);">+ [SLP_SMI_STS] = smihandler_southbridge_sleep,</span><br><span style="color: hsl(120, 100%, 40%);">+ [APM_SMI_STS] = smihandler_southbridge_apmc,</span><br><span> [PM1_STS_BIT] = smihandler_southbridge_pm1,</span><br><span> [GPE0_STS_BIT] = smihandler_southbridge_gpe0,</span><br><span> [GPIO_STS_BIT] = smihandler_southbridge_gpi,</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26138">change 26138</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26138"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 </div>
<div style="display:none"> Gerrit-Change-Number: 26138 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>