[coreboot-gerrit] Change in coreboot[master]: w530 initial work
Anonymous Coward (Code Review)
gerrit at coreboot.org
Mon May 7 17:09:57 CEST 2018
Anonymous Coward #1001983 has uploaded this change for review. ( https://review.coreboot.org/26136
Change subject: w530 initial work
......................................................................
w530 initial work
Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400
Signed-off-by: ch1p <me at ch1p.com>
---
A src/mainboard/lenovo/w530/Kconfig
A src/mainboard/lenovo/w530/Kconfig.name
A src/mainboard/lenovo/w530/Makefile.inc
A src/mainboard/lenovo/w530/acpi/ec.asl
A src/mainboard/lenovo/w530/acpi/platform.asl
A src/mainboard/lenovo/w530/acpi/superio.asl
A src/mainboard/lenovo/w530/acpi_tables.c
A src/mainboard/lenovo/w530/board_info.txt
A src/mainboard/lenovo/w530/cmos.default
A src/mainboard/lenovo/w530/cmos.layout
A src/mainboard/lenovo/w530/devicetree.cb
A src/mainboard/lenovo/w530/dsdt.asl
A src/mainboard/lenovo/w530/gpio.c
A src/mainboard/lenovo/w530/hda_verb.c
A src/mainboard/lenovo/w530/mainboard.c
A src/mainboard/lenovo/w530/romstage.c
A src/mainboard/lenovo/w530/smihandler.c
A src/mainboard/lenovo/w530/smihandler.c.bak
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_ivy.c
21 files changed, 1,234 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/26136/1
diff --git a/src/mainboard/lenovo/w530/Kconfig b/src/mainboard/lenovo/w530/Kconfig
new file mode 100644
index 0000000..3b848d5
--- /dev/null
+++ b/src/mainboard/lenovo/w530/Kconfig
@@ -0,0 +1,68 @@
+if BOARD_LENOVO_W530
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select CPU_INTEL_SOCKET_RPGA989
+ select DRIVERS_RICOH_RCE822
+ select EC_LENOVO_H8
+ select EC_LENOVO_PMH7
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_INT15
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SANDYBRIDGE_IVYBRIDGE_LVDS
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+ select ENABLE_VMX
+ select MAINBOARD_HAS_LPC_TPM
+ select DRIVERS_LENOVO_HYBRID_GRAPHICS
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config MAINBOARD_DIR
+ string
+ default lenovo/w530
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ThinkPad W530"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config VGA_BIOS_ID
+ string
+ default "8086,0166"
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0x21f6
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x17aa
+
+config DRAM_RESET_GATE_GPIO # FIXME: check this
+ int
+ default 10
+
+config MAX_CPUS
+ int
+ default 8
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+ int
+ default 2
+endif
diff --git a/src/mainboard/lenovo/w530/Kconfig.name b/src/mainboard/lenovo/w530/Kconfig.name
new file mode 100644
index 0000000..2a7b740
--- /dev/null
+++ b/src/mainboard/lenovo/w530/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LENOVO_W530
+ bool "ThinkPad W530"
diff --git a/src/mainboard/lenovo/w530/Makefile.inc b/src/mainboard/lenovo/w530/Makefile.inc
new file mode 100644
index 0000000..db5d725
--- /dev/null
+++ b/src/mainboard/lenovo/w530/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += gpio.c
+smm-y += smihandler.c
diff --git a/src/mainboard/lenovo/w530/acpi/ec.asl b/src/mainboard/lenovo/w530/acpi/ec.asl
new file mode 100644
index 0000000..c3569e8
--- /dev/null
+++ b/src/mainboard/lenovo/w530/acpi/ec.asl
@@ -0,0 +1 @@
+#include <ec/lenovo/h8/acpi/ec.asl>
diff --git a/src/mainboard/lenovo/w530/acpi/platform.asl b/src/mainboard/lenovo/w530/acpi/platform.asl
new file mode 100644
index 0000000..58ddbc6
--- /dev/null
+++ b/src/mainboard/lenovo/w530/acpi/platform.asl
@@ -0,0 +1,17 @@
+Method(_WAK,1)
+{
+ /* ME may not be up yet. */
+ Store (0, \_TZ.MEB1)
+ Store (0, \_TZ.MEB2)
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ /* from T530 */
+ \_SB.PCI0.LPCB.EC.MUTE(1)
+ \_SB.PCI0.LPCB.EC.USBP(0)
+
+ /* autoport */
+ \_SB.PCI0.LPCB.EC.RADI(0)
+}
diff --git a/src/mainboard/lenovo/w530/acpi/superio.asl b/src/mainboard/lenovo/w530/acpi/superio.asl
new file mode 100644
index 0000000..f2b35ba
--- /dev/null
+++ b/src/mainboard/lenovo/w530/acpi/superio.asl
@@ -0,0 +1 @@
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/w530/acpi_tables.c b/src/mainboard/lenovo/w530/acpi_tables.c
new file mode 100644
index 0000000..0e2920b
--- /dev/null
+++ b/src/mainboard/lenovo/w530/acpi_tables.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+/* FIXME: check this function. */
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+ gnvs->tcrt = 100;
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/lenovo/w530/board_info.txt b/src/mainboard/lenovo/w530/board_info.txt
new file mode 100644
index 0000000..4601a4a
--- /dev/null
+++ b/src/mainboard/lenovo/w530/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/lenovo/w530/cmos.default b/src/mainboard/lenovo/w530/cmos.default
new file mode 100644
index 0000000..76852cf
--- /dev/null
+++ b/src/mainboard/lenovo/w530/cmos.default
@@ -0,0 +1,17 @@
+boot_option=Fallback
+debug_level=Spew
+power_on_after_fail=Disable
+nmi=Enable
+volume=0x3
+first_battery=Primary
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+touchpad=Enable
+sata_mode=AHCI
+fn_ctrl_swap=Disable
+sticky_fn=Disable
+trackpoint=Enable
+backlight=Both
+hybrid_graphics_mode=Integrated Only
+usb_always_on=Disable
diff --git a/src/mainboard/lenovo/w530/cmos.layout b/src/mainboard/lenovo/w530/cmos.layout
new file mode 100644
index 0000000..7a9d27a
--- /dev/null
+++ b/src/mainboard/lenovo/w530/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+411 1 e 8 first_battery
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 touchpad
+415 1 e 1 wlan
+416 1 e 1 trackpoint
+417 1 e 1 fn_ctrl_swap
+418 1 e 1 sticky_fn
+419 2 e 13 usb_always_on
+421 1 e 9 sata_mode
+422 2 e 10 backlight
+
+# coreboot config options: cpu
+#424 8 r 0 unused
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+#437 3 r 0 unused
+
+440 8 h 0 volume
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+8 0 Secondary
+8 1 Primary
+9 0 AHCI
+9 1 Compatible
+10 0 Both
+10 1 Keyboard only
+10 2 Thinklight only
+10 3 None
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+12 0 Integrated Only
+12 1 Discrete Only
+13 0 Disable
+13 1 AC and battery
+13 2 AC only
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/lenovo/w530/devicetree.cb b/src/mainboard/lenovo/w530/devicetree.cb
new file mode 100644
index 0000000..e451b33
--- /dev/null
+++ b/src/mainboard/lenovo/w530/devicetree.cb
@@ -0,0 +1,179 @@
+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+ register "gfx.link_frequency_270_mhz" = "0"
+ register "gfx.ndid" = "3"
+ register "gfx.use_spread_spectrum_clock" = "0"
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "0"
+ register "gpu_dp_c_hotplug" = "0"
+ register "gpu_dp_d_hotplug" = "0"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "0"
+ register "gpu_panel_power_backlight_on_delay" = "0"
+ register "gpu_panel_power_cycle_delay" = "0"
+ register "gpu_panel_power_down_delay" = "0"
+ register "gpu_panel_power_up_delay" = "0"
+ register "gpu_pch_backlight" = "0x00000000"
+ device cpu_cluster 0x0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0x0 on
+ end
+ end
+ chip cpu/intel/model_206ax # FIXME: check all registers
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+ device lapic 0xacac off
+ end
+ end
+ end
+ device domain 0x0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "c2_latency" = "0x0065"
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c1601"
+ register "gen2_dec" = "0x000c15e1"
+ register "gen3_dec" = "0x00000000"
+ register "gen4_dec" = "0x000c06a1"
+ register "gpi13_routing" = "2"
+ register "gpi1_routing" = "2"
+ register "p_cnt_throttling_supported" = "1"
+ register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x13"
+ register "spi_lvscc" = "0x0"
+ register "spi_uvscc" = "0x0"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x04000201"
+ register "xhci_switchable_ports" = "0x0000000f"
+ device pci 14.0 on # USB 3.0 Controller
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 16.0 on # Management Engine Interface 1
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 16.1 off # Management Engine Interface 2
+ end
+ device pci 16.2 off # Management Engine IDE-R
+ end
+ device pci 16.3 on # Management Engine KT
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x17aa 0x21f3
+ end
+ device pci 1a.0 on # USB2 EHCI #2
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 1b.0 on # High Definition Audio Audio controller
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 1c.0 on # PCIe Port #1
+ subsystemid 0x17aa 0x21f6
+ chip drivers/ricoh/rce822 # Ricoh cardreader
+ register "disable_mask" = "0x83"
+ register "sdwppol" = "1"
+ device pci 00.0 on # Ricoh SD card reader
+ subsystemid 0x17aa 0x21f6
+ end
+ end
+ end
+ device pci 1c.1 on # PCIe Port #2
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 1c.2 on # PCIe Port #3
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 1c.3 off # PCIe Port #4
+ end
+ device pci 1c.4 off # PCIe Port #5
+ end
+ device pci 1c.5 off # PCIe Port #6
+ end
+ device pci 1c.6 off # PCIe Port #7
+ end
+ device pci 1c.7 off # PCIe Port #8
+ end
+ device pci 1d.0 on # USB2 EHCI #1
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 1e.0 off # PCI bridge
+ end
+ device pci 1f.0 on # LPC bridge PCI-LPC bridge
+ subsystemid 0x17aa 0x21f6
+ chip ec/lenovo/pmh7
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ device pnp ff.1 on # dummy
+ end
+ end
+ chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+ register "config0" = "0xa6"
+ register "config1" = "0x09"
+ register "config2" = "0xa0"
+ register "config3" = "0xc0"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0x3c"
+ register "event7_enable" = "0x01"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventb_enable" = "0x08"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x0d"
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+ end
+ end
+ device pci 1f.2 on # SATA Controller 1
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x17aa 0x21f6
+ chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
+ device i2c 54 on
+ end
+ device i2c 55 on
+ end
+ device i2c 56 on
+ end
+ device i2c 57 on
+ end
+ device i2c 5c on
+ end
+ device i2c 5d on
+ end
+ device i2c 5e on
+ end
+ device i2c 5f on
+ end
+ end
+ end
+ device pci 1f.5 off # SATA Controller 2
+ end
+ device pci 1f.6 off # Thermal
+ end
+ end
+ device pci 00.0 on # Host bridge Host bridge
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 01.0 on # PCIe Bridge for discrete graphics
+ subsystemid 0x17aa 0x21f6
+ end
+ device pci 02.0 on # Internal graphics VGA controller
+ subsystemid 0x17aa 0x21f5
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/w530/dsdt.asl b/src/mainboard/lenovo/w530/dsdt.asl
new file mode 100644
index 0000000..d1da55e
--- /dev/null
+++ b/src/mainboard/lenovo/w530/dsdt.asl
@@ -0,0 +1,31 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
+#define EC_LENOVO_H8_ME_WORKAROUND 1
+#define THINKPAD_EC_GPE 17
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/w530/gpio.c b/src/mainboard/lenovo/w530/gpio.c
new file mode 100644
index 0000000..8eb776b
--- /dev/null
+++ b/src/mainboard/lenovo/w530/gpio.c
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio43 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio65 = GPIO_DIR_INPUT,
+ .gpio66 = GPIO_DIR_INPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/lenovo/w530/hda_verb.c b/src/mainboard/lenovo/w530/hda_verb.c
new file mode 100644
index 0000000..f7e73ff
--- /dev/null
+++ b/src/mainboard/lenovo/w530/hda_verb.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */
+ 0x17aa2204, /* Subsystem ID */
+
+ 0x0000000b, /* Number of 4 dword sets */
+ /* NID 0x01: Subsystem ID. */
+ AZALIA_SUBVENDOR(0x0, 0x17aa2204),
+
+ /* NID 0x12. */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),
+
+ /* NID 0x14. */
+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
+
+ /* NID 0x15. */
+ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
+
+ /* NID 0x17. */
+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
+
+ /* NID 0x18. */
+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830),
+
+ /* NID 0x19. */
+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
+
+ /* NID 0x1a. */
+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
+
+ /* NID 0x1b. */
+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
+
+ /* NID 0x1d. */
+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205),
+
+ /* NID 0x1e. */
+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/w530/mainboard.c b/src/mainboard/lenovo/w530/mainboard.c
new file mode 100644
index 0000000..80a4fbb
--- /dev/null
+++ b/src/mainboard/lenovo/w530/mainboard.c
@@ -0,0 +1,20 @@
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/lenovo/h8/h8.h>
+
+static void mainboard_enable(device_t dev)
+{
+ /* FIXME: fix those values*/
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+void h8_mainboard_init_dock(void)
+{
+/* FIXME: fill this if needed. */
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/lenovo/w530/romstage.c b/src/mainboard/lenovo/w530/romstage.c
new file mode 100644
index 0000000..c636ba4
--- /dev/null
+++ b/src/mainboard/lenovo/w530/romstage.c
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit_native.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include <southbridge/intel/common/gpio.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
+
+static void hybrid_graphics_init(void)
+{
+ bool peg, igd;
+ u32 reg32;
+
+ early_hybrid_graphics(&igd, &peg);
+
+ /* Hide disabled devices */
+ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
+ reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD);
+
+ if (peg)
+ reg32 |= DEVEN_PEG10;
+
+ if (igd)
+ reg32 |= DEVEN_IGD;
+ else
+ /* Disable IGD VGA decode, no GTT or GFX stolen */
+ pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
+
+ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
+}
+
+void pch_enable_lpc(void)
+{
+ /* X230 EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
+
+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
+}
+
+//void pch_enable_lpc(void)
+//{
+// pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1601);
+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c15e1);
+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);
+// pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+//}
+
+void mainboard_rcba_config(void)
+{
+ RCBA32(BUC) = 0;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */
+ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */
+ { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */
+ { 1, 1, -1 }, /* P3: WWAN slot, no OC */
+ { 1, 1, 2 }, /* P4: yellow USB, OC 2 */
+ { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */
+ { 0, 0, -1 }, /* P6: color sensor(w530), no OC */
+ { 1, 2, -1 }, /* P7: docking, no OC */
+ { 1, 0, -1 }, /* P8: smart card reader, no OC */
+ { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */
+ { 1, 0, -1 }, /* P10: fingerprint reader, no OC */
+ { 1, 0, -1 }, /* P11: bluetooth, no OC. */
+ { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/
+ { 1, 1, -1 }, /* P13: camera, no OC */
+};
+
+/*const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+};*/
+
+void mainboard_early_init(int s3resume)
+{
+ hybrid_graphics_init();
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+/* FIXME: Put proper SPD map here. */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x52, id_only);
+ read_spd(&spd[2], 0x51, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/lenovo/w530/smihandler.c b/src/mainboard/lenovo/w530/smihandler.c
new file mode 100644
index 0000000..ba79e12
--- /dev/null
+++ b/src/mainboard/lenovo/w530/smihandler.c
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <southbridge/intel/common/pmutil.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+ if (value < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+ if (value > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
+ (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch (event) {
+ case 0x14:
+ /* brightness up */
+ mainboard_smi_brightness_up();
+ break;
+ case 0x15:
+ /* brightness down */
+ mainboard_smi_brightness_down();
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << GPE_EC_SCI))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route EC_SCI to SCI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route EC_SCI to SMI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ h8_usb_always_on();
+
+ if (slp_typ == 3) {
+ u8 ec_wake = ec_read(0x32);
+ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */
+ if (ec_wake & 0x14) {
+ /* Redirect EC WAKE GPE to SCI. */
+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/w530/smihandler.c.bak b/src/mainboard/lenovo/w530/smihandler.c.bak
new file mode 100644
index 0000000..88460be
--- /dev/null
+++ b/src/mainboard/lenovo/w530/smihandler.c.bak
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#define GPE_EC_SCI 1
+/* FIXME: check this */
+#define GPE_EC_WAKE 13
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ return 0;
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << GPE_EC_SCI))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route EC_SCI to SCI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route EC_SCI to SMI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (slp_typ == 3) {
+ u8 ec_wake = ec_read(0x32);
+ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */
+ if (ec_wake & 0x14) {
+ /* Redirect EC WAKE GPE to SCI. */
+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
+ }
+ }
+}
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index b31f280..fe4983f 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -330,6 +330,7 @@
me_uma_size = intel_early_me_uma_size();
printk(BIOS_DEBUG, "Starting native Platform init\n");
+ printk(BIOS_DEBUG, "[init_dram_ddr3] min_tck=%d\n", min_tck);
u32 reg_5d10;
@@ -361,6 +362,7 @@
}
ctrl_cached = NULL;
} else {
+ printk(BIOS_DEBUG, "[init_dram_ddr3] found cached ctrl\n");
ctrl_cached = rdev_mmap_full(&rdev);
}
@@ -400,6 +402,7 @@
memset(&ctrl, 0, sizeof(ctrl));
ctrl.mobile = mobile;
ctrl.tCK = min_tck;
+ printk(BIOS_DEBUG, "[init_dram_ddr3] ctrl.tCK set to min_tck\n");
/* Get architecture */
cpures = cpuid(1);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 5f6753f..b12db76 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -389,17 +389,52 @@
const struct northbridge_intel_sandybridge_config *cfg = NULL;
dev = dev_find_slot(0, HOST_BRIDGE);
- if (dev)
+ if (dev) {
cfg = dev->chip_info;
+ printk(BIOS_DEBUG,
+ "<raminit_common.c %s()>: cfg dump:\n"
+ " gpu_dp_b_hotplug address: %p\n"
+ " gpu_dp_b_hotplug = 0x%08x\n"
+ " gpu_dp_c_hotplug = 0x%08x\n"
+ " gpu_dp_d_hotplug = 0x%08x\n"
+ " gpu_panel_port_select = 0x%08x\n"
+ " gpu_panel_power_cycle_delay = 0x%08x\n"
+ " gpu_panel_power_up_delay = 0x%08x\n"
+ " gpu_panel_power_down_delay = 0x%08x\n"
+ " gpu_panel_power_backlight_on_delay = 0x%08x\n"
+ " gpu_panel_power_backlight_off_delay = 0x%08x\n"
+ " gpu_cpu_backlight = 0x%08x\n"
+ " gpu_pch_backlight = 0x%08x\n"
+ " max_mem_clock_mhz = 0x%08x\n",
+
+ __func__,
+ &(cfg->gpu_dp_b_hotplug),
+ cfg->gpu_dp_b_hotplug,
+ cfg->gpu_dp_c_hotplug,
+ cfg->gpu_dp_d_hotplug,
+ cfg->gpu_panel_port_select,
+ cfg->gpu_panel_power_cycle_delay,
+ cfg->gpu_panel_power_up_delay,
+ cfg->gpu_panel_power_down_delay,
+ cfg->gpu_panel_power_backlight_on_delay,
+ cfg->gpu_panel_power_backlight_off_delay,
+ cfg->gpu_cpu_backlight,
+ cfg->gpu_pch_backlight,
+ cfg->max_mem_clock_mhz);
+ }
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->max_mem_clock_mhz == 0) {
- if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
+ printk(BIOS_DEBUG, "[get_mem_min_tck] !cfg || cfg->max_mem_clock_mhz == 0\n");
+ if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) {
+ printk(BIOS_DEBUG, "[get_mem_min_tck] IGNORE_MAX_FUSES enabled, returning 1333MHz\n");
return TCK_1333MHZ;
+ }
rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
+ printk(BIOS_DEBUG, "[get_mem_min_tck] p1\n");
/* read Capabilities A Register DMFC bits */
reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
reg32 &= 0x7;
@@ -413,6 +448,7 @@
break;
}
} else {
+ printk(BIOS_DEBUG, "[get_mem_min_tck] p2\n");
/* read Capabilities B Register DMFC bits */
reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B);
reg32 = (reg32 >> 4) & 0x7;
@@ -430,8 +466,10 @@
break;
}
}
+ printk(BIOS_DEBUG, "[get_mem_min_tck] p3, returning DEFAULT_TCK\n");
return DEFAULT_TCK;
} else {
+ printk(BIOS_DEBUG, "[get_mem_min_tck] cfg->max_mem_clock_mhz=%d\n", cfg->max_mem_clock_mhz);
if (cfg->max_mem_clock_mhz >= 1066)
return TCK_1066MHZ;
else if (cfg->max_mem_clock_mhz >= 933)
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 19dea2f..74a1210 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -533,7 +533,8 @@
static void dram_freq(ramctr_timing * ctrl)
{
if (ctrl->tCK > TCK_400MHZ) {
- printk (BIOS_ERR, "DRAM frequency is under lowest supported "
+ printk(BIOS_DEBUG, "[dram_freq] forcing TCK_400MHZ, ctrl->tCK=%u\n", ctrl->tCK);
+ printk(BIOS_ERR, "DRAM frequency is under lowest supported "
"frequency (400 MHz). Increasing to 400 MHz as last resort");
ctrl->tCK = TCK_400MHZ;
}
@@ -641,6 +642,7 @@
printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n",
fast_boot);
+ printk(BIOS_DEBUG, "[try_init_dram_ddr3_ivy] tCK=%u\n", ctrl->tCK);
if (!fast_boot) {
/* Find fastest common supported parameters */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400
Gerrit-Change-Number: 26136
Gerrit-PatchSet: 1
Gerrit-Owner: Anonymous Coward #1001983
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