<p>Anonymous Coward #1001983 has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26136">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">w530 initial work<br><br>Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400<br>Signed-off-by: ch1p <me@ch1p.com><br>---<br>A src/mainboard/lenovo/w530/Kconfig<br>A src/mainboard/lenovo/w530/Kconfig.name<br>A src/mainboard/lenovo/w530/Makefile.inc<br>A src/mainboard/lenovo/w530/acpi/ec.asl<br>A src/mainboard/lenovo/w530/acpi/platform.asl<br>A src/mainboard/lenovo/w530/acpi/superio.asl<br>A src/mainboard/lenovo/w530/acpi_tables.c<br>A src/mainboard/lenovo/w530/board_info.txt<br>A src/mainboard/lenovo/w530/cmos.default<br>A src/mainboard/lenovo/w530/cmos.layout<br>A src/mainboard/lenovo/w530/devicetree.cb<br>A src/mainboard/lenovo/w530/dsdt.asl<br>A src/mainboard/lenovo/w530/gpio.c<br>A src/mainboard/lenovo/w530/hda_verb.c<br>A src/mainboard/lenovo/w530/mainboard.c<br>A src/mainboard/lenovo/w530/romstage.c<br>A src/mainboard/lenovo/w530/smihandler.c<br>A src/mainboard/lenovo/w530/smihandler.c.bak<br>M src/northbridge/intel/sandybridge/raminit.c<br>M src/northbridge/intel/sandybridge/raminit_common.c<br>M src/northbridge/intel/sandybridge/raminit_ivy.c<br>21 files changed, 1,234 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/26136/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/lenovo/w530/Kconfig b/src/mainboard/lenovo/w530/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..3b848d5</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/Kconfig</span><br><span>@@ -0,0 +1,68 @@</span><br><span style="color: hsl(120, 100%, 40%);">+if BOARD_LENOVO_W530</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_SPECIFIC_OPTIONS # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool y</span><br><span style="color: hsl(120, 100%, 40%);">+ select BOARD_ROMSIZE_KB_12288</span><br><span style="color: hsl(120, 100%, 40%);">+ select CPU_INTEL_SOCKET_RPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_RICOH_RCE822</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_LENOVO_H8</span><br><span style="color: hsl(120, 100%, 40%);">+ select EC_LENOVO_PMH7</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_RESUME</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_ACPI_TABLES</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_CMOS_DEFAULT</span><br><span style="color: hsl(120, 100%, 40%);">+ select HAVE_OPTION_TABLE</span><br><span style="color: hsl(120, 100%, 40%);">+ select INTEL_INT15</span><br><span style="color: hsl(120, 100%, 40%);">+ select NORTHBRIDGE_INTEL_IVYBRIDGE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SANDYBRIDGE_IVYBRIDGE_LVDS</span><br><span style="color: hsl(120, 100%, 40%);">+ select SERIRQ_CONTINUOUS_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOUTHBRIDGE_INTEL_C216</span><br><span style="color: hsl(120, 100%, 40%);">+ select SYSTEM_TYPE_LAPTOP</span><br><span style="color: hsl(120, 100%, 40%);">+ select USE_NATIVE_RAMINIT</span><br><span style="color: hsl(120, 100%, 40%);">+ select ENABLE_VMX</span><br><span style="color: hsl(120, 100%, 40%);">+ select MAINBOARD_HAS_LPC_TPM</span><br><span style="color: hsl(120, 100%, 40%);">+ select DRIVERS_LENOVO_HYBRID_GRAPHICS</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HAVE_IFD_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config HAVE_ME_BIN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_DIR</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default lenovo/w530</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PART_NUMBER</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "ThinkPad W530"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_FILE</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "pci8086,0166.rom"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VGA_BIOS_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ string</span><br><span style="color: hsl(120, 100%, 40%);">+ default "8086,0166"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0x17aa</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config DRAM_RESET_GATE_GPIO # FIXME: check this</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config MAX_CPUS</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config USBDEBUG_HCD_INDEX # FIXME: check this</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 2</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span>diff --git a/src/mainboard/lenovo/w530/Kconfig.name b/src/mainboard/lenovo/w530/Kconfig.name</span><br><span>new file mode 100644</span><br><span>index 0000000..2a7b740</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/Kconfig.name</span><br><span>@@ -0,0 +1,2 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config BOARD_LENOVO_W530</span><br><span style="color: hsl(120, 100%, 40%);">+ bool "ThinkPad W530"</span><br><span>diff --git a/src/mainboard/lenovo/w530/Makefile.inc b/src/mainboard/lenovo/w530/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..db5d725</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/Makefile.inc</span><br><span>@@ -0,0 +1,17 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += gpio.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-y += smihandler.c</span><br><span>diff --git a/src/mainboard/lenovo/w530/acpi/ec.asl b/src/mainboard/lenovo/w530/acpi/ec.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..c3569e8</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/acpi/ec.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/lenovo/h8/acpi/ec.asl></span><br><span>diff --git a/src/mainboard/lenovo/w530/acpi/platform.asl b/src/mainboard/lenovo/w530/acpi/platform.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..58ddbc6</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/acpi/platform.asl</span><br><span>@@ -0,0 +1,17 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_WAK,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* ME may not be up yet. */</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, \_TZ.MEB1)</span><br><span style="color: hsl(120, 100%, 40%);">+ Store (0, \_TZ.MEB2)</span><br><span style="color: hsl(120, 100%, 40%);">+ Return(Package(){0,0})</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+Method(_PTS,1)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* from T530 */</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC.MUTE(1)</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC.USBP(0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* autoport */</span><br><span style="color: hsl(120, 100%, 40%);">+ \_SB.PCI0.LPCB.EC.RADI(0)</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/w530/acpi/superio.asl b/src/mainboard/lenovo/w530/acpi/superio.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..f2b35ba</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/acpi/superio.asl</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/pc80/pc/ps2_controller.asl></span><br><span>diff --git a/src/mainboard/lenovo/w530/acpi_tables.c b/src/mainboard/lenovo/w530/acpi_tables.c</span><br><span>new file mode 100644</span><br><span>index 0000000..0e2920b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/acpi_tables.c</span><br><span>@@ -0,0 +1,49 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <types.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cbmem.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/ioapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpigen.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/smp/mpspec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* FIXME: check this function. */</span><br><span style="color: hsl(120, 100%, 40%);">+void acpi_create_gnvs(global_nvs_t *gnvs)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S3 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s3u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable USB ports in S5 by default */</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u0 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->s5u1 = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // the lid is open by default.</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->lids = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tcrt = 100;</span><br><span style="color: hsl(120, 100%, 40%);">+ gnvs->tpsv = 90;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/w530/board_info.txt b/src/mainboard/lenovo/w530/board_info.txt</span><br><span>new file mode 100644</span><br><span>index 0000000..4601a4a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/board_info.txt</span><br><span>@@ -0,0 +1,6 @@</span><br><span style="color: hsl(120, 100%, 40%);">+Category: laptop</span><br><span style="color: hsl(120, 100%, 40%);">+ROM package: SOIC-8</span><br><span style="color: hsl(120, 100%, 40%);">+ROM protocol: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ROM socketed: n</span><br><span style="color: hsl(120, 100%, 40%);">+Flashrom support: y</span><br><span style="color: hsl(120, 100%, 40%);">+Release year: 2012</span><br><span>diff --git a/src/mainboard/lenovo/w530/cmos.default b/src/mainboard/lenovo/w530/cmos.default</span><br><span>new file mode 100644</span><br><span>index 0000000..76852cf</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/cmos.default</span><br><span>@@ -0,0 +1,17 @@</span><br><span style="color: hsl(120, 100%, 40%);">+boot_option=Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+debug_level=Spew</span><br><span style="color: hsl(120, 100%, 40%);">+power_on_after_fail=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+nmi=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+volume=0x3</span><br><span style="color: hsl(120, 100%, 40%);">+first_battery=Primary</span><br><span style="color: hsl(120, 100%, 40%);">+bluetooth=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+wwan=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+wlan=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+touchpad=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+sata_mode=AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+fn_ctrl_swap=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+sticky_fn=Disable</span><br><span style="color: hsl(120, 100%, 40%);">+trackpoint=Enable</span><br><span style="color: hsl(120, 100%, 40%);">+backlight=Both</span><br><span style="color: hsl(120, 100%, 40%);">+hybrid_graphics_mode=Integrated Only</span><br><span style="color: hsl(120, 100%, 40%);">+usb_always_on=Disable</span><br><span>diff --git a/src/mainboard/lenovo/w530/cmos.layout b/src/mainboard/lenovo/w530/cmos.layout</span><br><span>new file mode 100644</span><br><span>index 0000000..7a9d27a</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/cmos.layout</span><br><span>@@ -0,0 +1,139 @@</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2007-2008 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+## Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+## it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+## the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+## This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+## but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+## GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+##</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+entries</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register A</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register B</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register C</span><br><span style="color: hsl(120, 100%, 40%);">+#96 4 r 0 status_c_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#100 1 r 0 uf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#101 1 r 0 af_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#102 1 r 0 pf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+#103 1 r 0 irqf_flag</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Status Register D</span><br><span style="color: hsl(120, 100%, 40%);">+#104 7 r 0 status_d_rsvd</span><br><span style="color: hsl(120, 100%, 40%);">+#111 1 r 0 valid_cmos_ram</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# Diagnostic Status Register</span><br><span style="color: hsl(120, 100%, 40%);">+#112 8 r 0 diag_rsvd1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+0 120 r 0 reserved_memory</span><br><span style="color: hsl(120, 100%, 40%);">+#120 264 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# RTC_BOOT_BYTE (coreboot hardcoded)</span><br><span style="color: hsl(120, 100%, 40%);">+384 1 e 4 boot_option</span><br><span style="color: hsl(120, 100%, 40%);">+388 4 h 0 reboot_counter</span><br><span style="color: hsl(120, 100%, 40%);">+#390 2 r 0 unused?</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: console</span><br><span style="color: hsl(120, 100%, 40%);">+#392 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+395 4 e 6 debug_level</span><br><span style="color: hsl(120, 100%, 40%);">+#399 1 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#400 8 r 0 reserved for century byte</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: southbridge</span><br><span style="color: hsl(120, 100%, 40%);">+408 1 e 1 nmi</span><br><span style="color: hsl(120, 100%, 40%);">+409 2 e 7 power_on_after_fail</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: EC</span><br><span style="color: hsl(120, 100%, 40%);">+411 1 e 8 first_battery</span><br><span style="color: hsl(120, 100%, 40%);">+412 1 e 1 bluetooth</span><br><span style="color: hsl(120, 100%, 40%);">+413 1 e 1 wwan</span><br><span style="color: hsl(120, 100%, 40%);">+414 1 e 1 touchpad</span><br><span style="color: hsl(120, 100%, 40%);">+415 1 e 1 wlan</span><br><span style="color: hsl(120, 100%, 40%);">+416 1 e 1 trackpoint</span><br><span style="color: hsl(120, 100%, 40%);">+417 1 e 1 fn_ctrl_swap</span><br><span style="color: hsl(120, 100%, 40%);">+418 1 e 1 sticky_fn</span><br><span style="color: hsl(120, 100%, 40%);">+419 2 e 13 usb_always_on</span><br><span style="color: hsl(120, 100%, 40%);">+421 1 e 9 sata_mode</span><br><span style="color: hsl(120, 100%, 40%);">+422 2 e 10 backlight</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: cpu</span><br><span style="color: hsl(120, 100%, 40%);">+#424 8 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: northbridge</span><br><span style="color: hsl(120, 100%, 40%);">+432 3 e 11 gfx_uma_size</span><br><span style="color: hsl(120, 100%, 40%);">+435 2 e 12 hybrid_graphics_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#437 3 r 0 unused</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+440 8 h 0 volume</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# SandyBridge MRC Scrambler Seed values</span><br><span style="color: hsl(120, 100%, 40%);">+896 32 r 0 mrc_scrambler_seed</span><br><span style="color: hsl(120, 100%, 40%);">+928 32 r 0 mrc_scrambler_seed_s3</span><br><span style="color: hsl(120, 100%, 40%);">+960 16 r 0 mrc_scrambler_seed_chk</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# coreboot config options: check sums</span><br><span style="color: hsl(120, 100%, 40%);">+984 16 h 0 check_sum</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+enumerations</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ID value text</span><br><span style="color: hsl(120, 100%, 40%);">+1 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+1 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 0 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+2 1 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+4 0 Fallback</span><br><span style="color: hsl(120, 100%, 40%);">+4 1 Normal</span><br><span style="color: hsl(120, 100%, 40%);">+6 0 Emergency</span><br><span style="color: hsl(120, 100%, 40%);">+6 1 Alert</span><br><span style="color: hsl(120, 100%, 40%);">+6 2 Critical</span><br><span style="color: hsl(120, 100%, 40%);">+6 3 Error</span><br><span style="color: hsl(120, 100%, 40%);">+6 4 Warning</span><br><span style="color: hsl(120, 100%, 40%);">+6 5 Notice</span><br><span style="color: hsl(120, 100%, 40%);">+6 6 Info</span><br><span style="color: hsl(120, 100%, 40%);">+6 7 Debug</span><br><span style="color: hsl(120, 100%, 40%);">+6 8 Spew</span><br><span style="color: hsl(120, 100%, 40%);">+7 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+7 1 Enable</span><br><span style="color: hsl(120, 100%, 40%);">+7 2 Keep</span><br><span style="color: hsl(120, 100%, 40%);">+8 0 Secondary</span><br><span style="color: hsl(120, 100%, 40%);">+8 1 Primary</span><br><span style="color: hsl(120, 100%, 40%);">+9 0 AHCI</span><br><span style="color: hsl(120, 100%, 40%);">+9 1 Compatible</span><br><span style="color: hsl(120, 100%, 40%);">+10 0 Both</span><br><span style="color: hsl(120, 100%, 40%);">+10 1 Keyboard only</span><br><span style="color: hsl(120, 100%, 40%);">+10 2 Thinklight only</span><br><span style="color: hsl(120, 100%, 40%);">+10 3 None</span><br><span style="color: hsl(120, 100%, 40%);">+11 0 32M</span><br><span style="color: hsl(120, 100%, 40%);">+11 1 64M</span><br><span style="color: hsl(120, 100%, 40%);">+11 2 96M</span><br><span style="color: hsl(120, 100%, 40%);">+11 3 128M</span><br><span style="color: hsl(120, 100%, 40%);">+11 4 160M</span><br><span style="color: hsl(120, 100%, 40%);">+11 5 192M</span><br><span style="color: hsl(120, 100%, 40%);">+11 6 224M</span><br><span style="color: hsl(120, 100%, 40%);">+12 0 Integrated Only</span><br><span style="color: hsl(120, 100%, 40%);">+12 1 Discrete Only</span><br><span style="color: hsl(120, 100%, 40%);">+13 0 Disable</span><br><span style="color: hsl(120, 100%, 40%);">+13 1 AC and battery</span><br><span style="color: hsl(120, 100%, 40%);">+13 2 AC only</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+# -----------------------------------------------------------------</span><br><span style="color: hsl(120, 100%, 40%);">+checksums</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+checksum 392 447 984</span><br><span>diff --git a/src/mainboard/lenovo/w530/devicetree.cb b/src/mainboard/lenovo/w530/devicetree.cb</span><br><span>new file mode 100644</span><br><span>index 0000000..e451b33</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/devicetree.cb</span><br><span>@@ -0,0 +1,179 @@</span><br><span style="color: hsl(120, 100%, 40%);">+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.link_frequency_270_mhz" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.ndid" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gfx.use_spread_spectrum_clock" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_cpu_backlight" = "0x00000000"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_b_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_c_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_dp_d_hotplug" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_port_select" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_off_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_backlight_on_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_cycle_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_down_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_panel_power_up_delay" = "0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpu_pch_backlight" = "0x00000000"</span><br><span style="color: hsl(120, 100%, 40%);">+ device cpu_cluster 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/socket_rPGA989</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip cpu/intel/model_206ax # FIXME: check all registers</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_acpower" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c1_battery" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_acpower" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_battery" = "3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_acpower" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c3_battery" = "5"</span><br><span style="color: hsl(120, 100%, 40%);">+ device lapic 0xacac off</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device domain 0x0 on</span><br><span style="color: hsl(120, 100%, 40%);">+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH</span><br><span style="color: hsl(120, 100%, 40%);">+ register "c2_latency" = "0x0065"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "docking_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen1_dec" = "0x007c1601"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen2_dec" = "0x000c15e1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen3_dec" = "0x00000000"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gen4_dec" = "0x000c06a1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi13_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "gpi1_routing" = "2"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "p_cnt_throttling_supported" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "pcie_port_coalesce" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_interface_speed_support" = "0x3"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sata_port_map" = "0x13"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_lvscc" = "0x0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "spi_uvscc" = "0x0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "superspeed_capable_ports" = "0x0000000f"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_overcurrent_mapping" = "0x04000201"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "xhci_switchable_ports" = "0x0000000f"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 14.0 on # USB 3.0 Controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.0 on # Management Engine Interface 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.1 off # Management Engine Interface 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.2 off # Management Engine IDE-R</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 16.3 on # Management Engine KT</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 19.0 on # Intel Gigabit Ethernet</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f3</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1a.0 on # USB2 EHCI #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1b.0 on # High Definition Audio Audio controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.0 on # PCIe Port #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/ricoh/rce822 # Ricoh cardreader</span><br><span style="color: hsl(120, 100%, 40%);">+ register "disable_mask" = "0x83"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "sdwppol" = "1"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Ricoh SD card reader</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.1 on # PCIe Port #2</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.2 on # PCIe Port #3</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.3 off # PCIe Port #4</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.4 off # PCIe Port #5</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.5 off # PCIe Port #6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.6 off # PCIe Port #7</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1c.7 off # PCIe Port #8</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1d.0 on # USB2 EHCI #1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1e.0 off # PCI bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.0 on # LPC bridge PCI-LPC bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/pmh7</span><br><span style="color: hsl(120, 100%, 40%);">+ register "backlight_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "dock_event_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.1 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask0" = "0x00"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "beepmask1" = "0x86"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config0" = "0xa6"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config1" = "0x09"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config2" = "0xa0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "config3" = "0xc0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event2_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event3_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event4_enable" = "0xd0"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event5_enable" = "0x3c"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event7_enable" = "0x01"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event8_enable" = "0x7b"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "event9_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventb_enable" = "0x08"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventc_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "eventd_enable" = "0xff"</span><br><span style="color: hsl(120, 100%, 40%);">+ register "evente_enable" = "0x0d"</span><br><span style="color: hsl(120, 100%, 40%);">+ device pnp ff.2 on # dummy</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x60 = 0x62</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x62 = 0x66</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x64 = 0x1600</span><br><span style="color: hsl(120, 100%, 40%);">+ io 0x66 = 0x1604</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.2 on # SATA Controller 1</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.3 on # SMBus</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 54 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 55 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 56 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 57 on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5c on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5d on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5e on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device i2c 5f on</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.5 off # SATA Controller 2</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 1f.6 off # Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 00.0 on # Host bridge Host bridge</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 01.0 on # PCIe Bridge for discrete graphics</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f6</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ device pci 02.0 on # Internal graphics VGA controller</span><br><span style="color: hsl(120, 100%, 40%);">+ subsystemid 0x17aa 0x21f5</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+ end</span><br><span style="color: hsl(120, 100%, 40%);">+end</span><br><span>diff --git a/src/mainboard/lenovo/w530/dsdt.asl b/src/mainboard/lenovo/w530/dsdt.asl</span><br><span>new file mode 100644</span><br><span>index 0000000..d1da55e</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/dsdt.asl</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB</span><br><span style="color: hsl(120, 100%, 40%);">+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB</span><br><span style="color: hsl(120, 100%, 40%);">+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0</span><br><span style="color: hsl(120, 100%, 40%);">+#define EC_LENOVO_H8_ME_WORKAROUND 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define THINKPAD_EC_GPE 17</span><br><span style="color: hsl(120, 100%, 40%);">+DefinitionBlock(</span><br><span style="color: hsl(120, 100%, 40%);">+ "dsdt.aml",</span><br><span style="color: hsl(120, 100%, 40%);">+ "DSDT",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, // DSDT revision: ACPI v3.0</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREv4", // OEM id</span><br><span style="color: hsl(120, 100%, 40%);">+ "COREBOOT", // OEM table id</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x20141018 // OEM revision</span><br><span style="color: hsl(120, 100%, 40%);">+)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ // Some generic macros</span><br><span style="color: hsl(120, 100%, 40%);">+ #include "acpi/platform.asl"</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <cpu/intel/model_206ax/acpi/cpu.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/platform.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ /* global NVS and variables. */</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Scope (\_SB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ Device (PCI0)</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span style="color: hsl(120, 100%, 40%);">+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ #include <southbridge/intel/bd82x6x/acpi/pch.asl></span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/w530/gpio.c b/src/mainboard/lenovo/w530/gpio.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8eb776b</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/gpio.c</span><br><span>@@ -0,0 +1,219 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio9 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio11 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio12 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio14 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio16 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio18 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio19 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio20 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio23 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio25 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio26 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio30 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio31 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio0 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio2 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio3 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio4 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio5 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio6 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio7 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio17 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio21 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio27 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio8 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio10 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio15 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio22 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio28 = GPIO_LEVEL_LOW,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio29 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio24 = GPIO_RESET_RSMRST,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_invert = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio1 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio13 = GPIO_INVERT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set1 pch_gpio_set1_blink = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio32 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio40 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio41 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio42 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio44 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio45 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio46 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio47 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio56 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio58 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio59 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio60 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio61 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio62 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio63 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio34 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio35 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio36 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio37 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio38 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio39 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio48 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio49 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio50 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio54 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_DIR_OUTPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio57 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio33 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio43 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio51 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio52 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio53 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio55 = GPIO_LEVEL_HIGH,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set2 pch_gpio_set2_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_mode = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_MODE_GPIO,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio72 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio73 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio74 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio75 = GPIO_MODE_NATIVE,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_direction = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio64 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio65 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio66 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio67 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio68 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio69 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio70 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+ .gpio71 = GPIO_DIR_INPUT,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_level = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static const struct pch_gpio_set3 pch_gpio_set3_reset = {</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct pch_gpio_map mainboard_gpio_map = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .set1 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set1_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set1_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set1_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .blink = &pch_gpio_set1_blink,</span><br><span style="color: hsl(120, 100%, 40%);">+ .invert = &pch_gpio_set1_invert,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set1_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set2 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set2_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set2_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set2_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set2_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ .set3 = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .mode = &pch_gpio_set3_mode,</span><br><span style="color: hsl(120, 100%, 40%);">+ .direction = &pch_gpio_set3_direction,</span><br><span style="color: hsl(120, 100%, 40%);">+ .level = &pch_gpio_set3_level,</span><br><span style="color: hsl(120, 100%, 40%);">+ .reset = &pch_gpio_set3_reset,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/w530/hda_verb.c b/src/mainboard/lenovo/w530/hda_verb.c</span><br><span>new file mode 100644</span><br><span>index 0000000..f7e73ff</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/hda_verb.c</span><br><span>@@ -0,0 +1,61 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/azalia_device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 cim_verb_data[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x17aa2204, /* Subsystem ID */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x0000000b, /* Number of 4 dword sets */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x01: Subsystem ID. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_SUBVENDOR(0x0, 0x17aa2204),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x12. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x14. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x15. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x17. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x18. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x19. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1a. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1b. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1d. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205),</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* NID 0x1e. */</span><br><span style="color: hsl(120, 100%, 40%);">+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const u32 pc_beep_verbs[0] = {};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+AZALIA_ARRAY_SIZES;</span><br><span>diff --git a/src/mainboard/lenovo/w530/mainboard.c b/src/mainboard/lenovo/w530/mainboard.c</span><br><span>new file mode 100644</span><br><span>index 0000000..80a4fbb</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/mainboard.c</span><br><span>@@ -0,0 +1,20 @@</span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/intel/gma/int15.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/lenovo/h8/h8.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_enable(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* FIXME: fix those values*/</span><br><span style="color: hsl(120, 100%, 40%);">+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,</span><br><span style="color: hsl(120, 100%, 40%);">+ GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void h8_mainboard_init_dock(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+/* FIXME: fill this if needed. */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+struct chip_operations mainboard_ops = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span>diff --git a/src/mainboard/lenovo/w530/romstage.c b/src/mainboard/lenovo/w530/romstage.c</span><br><span>new file mode 100644</span><br><span>index 0000000..c636ba4</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/romstage.c</span><br><span>@@ -0,0 +1,139 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <stdint.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/byteorder.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pci_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/pnp_def.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/lapic.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/acpi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "northbridge/intel/sandybridge/sandybridge.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "northbridge/intel/sandybridge/raminit_native.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include "southbridge/intel/bd82x6x/pch.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/gpio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/cpu.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void hybrid_graphics_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ bool peg, igd;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ early_hybrid_graphics(&igd, &peg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Hide disabled devices */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (peg)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= DEVEN_PEG10;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (igd)</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= DEVEN_IGD;</span><br><span style="color: hsl(120, 100%, 40%);">+ else</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Disable IGD VGA decode, no GTT or GFX stolen */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* X230 EC Decode Range Port60/64, Port62/66 */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable EC, PS/2 Keyboard/Mouse */</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config16(PCH_LPC_DEV, LPC_EN,</span><br><span style="color: hsl(120, 100%, 40%);">+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+//void pch_enable_lpc(void)</span><br><span style="color: hsl(120, 100%, 40%);">+//{</span><br><span style="color: hsl(120, 100%, 40%);">+// pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);</span><br><span style="color: hsl(120, 100%, 40%);">+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1601);</span><br><span style="color: hsl(120, 100%, 40%);">+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c15e1);</span><br><span style="color: hsl(120, 100%, 40%);">+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);</span><br><span style="color: hsl(120, 100%, 40%);">+// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);</span><br><span style="color: hsl(120, 100%, 40%);">+// pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);</span><br><span style="color: hsl(120, 100%, 40%);">+//}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_rcba_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ RCBA32(BUC) = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* P3: WWAN slot, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 2 }, /* P4: yellow USB, OC 2 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 0, 0, -1 }, /* P6: color sensor(w530), no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 2, -1 }, /* P7: docking, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P8: smart card reader, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P10: fingerprint reader, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 }, /* P11: bluetooth, no OC. */</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 1, -1 }, /* P13: camera, no OC */</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*const struct southbridge_usb_port mainboard_usb_ports[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { 1, 0, -1 },</span><br><span style="color: hsl(120, 100%, 40%);">+};*/</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_early_init(int s3resume)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ hybrid_graphics_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_config_superio(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* FIXME: Put proper SPD map here. */</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_get_spd(spd_raw_data *spd, bool id_only)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[0], 0x50, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[1], 0x52, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[2], 0x51, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+ read_spd(&spd[3], 0x53, id_only);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/w530/smihandler.c b/src/mainboard/lenovo/w530/smihandler.c</span><br><span>new file mode 100644</span><br><span>index 0000000..ba79e12</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/smihandler.c</span><br><span>@@ -0,0 +1,119 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/acpi/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <pc80/mc146818rtc.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/lenovo/h8/h8.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/nvs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/me.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/common/pmutil.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <northbridge/intel/sandybridge/sandybridge.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/model_206ax/model_206ax.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_SCI 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_WAKE 13</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_smi_brightness_up(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (value < 0xf0)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_smi_brightness_down(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (value > 0x10)</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,</span><br><span style="color: hsl(120, 100%, 40%);">+ (value - 0x10) & 0xf0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_smi_handle_ec_sci(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 status = inb(EC_SC);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 event;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(status & EC_SCI_EVT))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ event = ec_query();</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "EC event %02x\n", event);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (event) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x14:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* brightness up */</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_smi_brightness_up();</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case 0x15:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* brightness down */</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_smi_brightness_down();</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_gpi(u32 gpi_sts)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpi_sts & (1 << GPE_EC_SCI))</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_smi_handle_ec_sci();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_smi_apmc(u8 data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (data) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case APM_CNT_ACPI_ENABLE:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* use 0x1600/0x1604 to prevent races with userspace */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_set_ports(0x1604, 0x1600);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* route EC_SCI to SCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* discard all events, and enable attention */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_write(0x80, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case APM_CNT_ACPI_DISABLE:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't</span><br><span style="color: hsl(120, 100%, 40%);">+ provide a EC query function */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_set_ports(0x66, 0x62);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* route EC_SCI to SMI */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* discard all events, and enable attention */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_write(0x80, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_sleep(u8 slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ h8_usb_always_on();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (slp_typ == 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ec_wake = ec_read(0x32);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ec_wake & 0x14) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Redirect EC WAKE GPE to SCI. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/mainboard/lenovo/w530/smihandler.c.bak b/src/mainboard/lenovo/w530/smihandler.c.bak</span><br><span>new file mode 100644</span><br><span>index 0000000..88460be</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/lenovo/w530/smihandler.c.bak</span><br><span>@@ -0,0 +1,103 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2008-2009 coresystems GmbH</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2014 Vladimir Serbinenko</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or</span><br><span style="color: hsl(120, 100%, 40%);">+ * modify it under the terms of the GNU General Public License as</span><br><span style="color: hsl(120, 100%, 40%);">+ * published by the Free Software Foundation; version 2 of</span><br><span style="color: hsl(120, 100%, 40%);">+ * the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/x86/smm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/acpi/ec.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <ec/lenovo/h8/h8.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <delay.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <southbridge/intel/bd82x6x/pch.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_SCI 1</span><br><span style="color: hsl(120, 100%, 40%);">+/* FIXME: check this */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPE_EC_WAKE 13</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_smm_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "initializing SMI\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable 0x1600/0x1600 register pair */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_set_bit(0x00, 0x05);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_io_trap_handler(int smif)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ static int smm_initialized;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!smm_initialized) {</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_smm_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ smm_initialized = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_smi_handle_ec_sci(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 status = inb(EC_SC);</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 event;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!(status & EC_SCI_EVT))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ event = ec_query();</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "EC event %02x\n", event);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_gpi(u32 gpi_sts)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gpi_sts & (1 << GPE_EC_SCI))</span><br><span style="color: hsl(120, 100%, 40%);">+ mainboard_smi_handle_ec_sci();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int mainboard_smi_apmc(u8 data)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (data) {</span><br><span style="color: hsl(120, 100%, 40%);">+ case APM_CNT_ACPI_ENABLE:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* use 0x1600/0x1604 to prevent races with userspace */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_set_ports(0x1604, 0x1600);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* route EC_SCI to SCI */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* discard all events, and enable attention */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_write(0x80, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ case APM_CNT_ACPI_DISABLE:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't</span><br><span style="color: hsl(120, 100%, 40%);">+ provide a EC query function */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_set_ports(0x66, 0x62);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* route EC_SCI to SMI */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* discard all events, and enable attention */</span><br><span style="color: hsl(120, 100%, 40%);">+ ec_write(0x80, 0x01);</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ default:</span><br><span style="color: hsl(120, 100%, 40%);">+ break;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_smi_sleep(u8 slp_typ)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (slp_typ == 3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 ec_wake = ec_read(0x32);</span><br><span style="color: hsl(120, 100%, 40%);">+ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (ec_wake & 0x14) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Redirect EC WAKE GPE to SCI. */</span><br><span style="color: hsl(120, 100%, 40%);">+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>index b31f280..fe4983f 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit.c</span><br><span>@@ -330,6 +330,7 @@</span><br><span> me_uma_size = intel_early_me_uma_size();</span><br><span> </span><br><span> printk(BIOS_DEBUG, "Starting native Platform init\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[init_dram_ddr3] min_tck=%d\n", min_tck);</span><br><span> </span><br><span> u32 reg_5d10;</span><br><span> </span><br><span>@@ -361,6 +362,7 @@</span><br><span> }</span><br><span> ctrl_cached = NULL;</span><br><span> } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[init_dram_ddr3] found cached ctrl\n");</span><br><span> ctrl_cached = rdev_mmap_full(&rdev);</span><br><span> }</span><br><span> </span><br><span>@@ -400,6 +402,7 @@</span><br><span> memset(&ctrl, 0, sizeof(ctrl));</span><br><span> ctrl.mobile = mobile;</span><br><span> ctrl.tCK = min_tck;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[init_dram_ddr3] ctrl.tCK set to min_tck\n");</span><br><span> </span><br><span> /* Get architecture */</span><br><span> cpures = cpuid(1);</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>index 5f6753f..b12db76 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_common.c</span><br><span>@@ -389,17 +389,52 @@</span><br><span> const struct northbridge_intel_sandybridge_config *cfg = NULL;</span><br><span> </span><br><span> dev = dev_find_slot(0, HOST_BRIDGE);</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev)</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev) {</span><br><span> cfg = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG,</span><br><span style="color: hsl(120, 100%, 40%);">+ "<raminit_common.c %s()>: cfg dump:\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_dp_b_hotplug address: %p\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_dp_b_hotplug = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_dp_c_hotplug = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_dp_d_hotplug = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_panel_port_select = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_panel_power_cycle_delay = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_panel_power_up_delay = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_panel_power_down_delay = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_panel_power_backlight_on_delay = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_panel_power_backlight_off_delay = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_cpu_backlight = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " gpu_pch_backlight = 0x%08x\n"</span><br><span style="color: hsl(120, 100%, 40%);">+ " max_mem_clock_mhz = 0x%08x\n",</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__,</span><br><span style="color: hsl(120, 100%, 40%);">+ &(cfg->gpu_dp_b_hotplug),</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_dp_b_hotplug,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_dp_c_hotplug,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_dp_d_hotplug,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_panel_port_select,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_panel_power_cycle_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_panel_power_up_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_panel_power_down_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_panel_power_backlight_on_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_panel_power_backlight_off_delay,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_cpu_backlight,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->gpu_pch_backlight,</span><br><span style="color: hsl(120, 100%, 40%);">+ cfg->max_mem_clock_mhz);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> /* If this is zero, it just means devicetree.cb didn't set it */</span><br><span> if (!cfg || cfg->max_mem_clock_mhz == 0) {</span><br><span style="color: hsl(0, 100%, 40%);">- if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[get_mem_min_tck] !cfg || cfg->max_mem_clock_mhz == 0\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[get_mem_min_tck] IGNORE_MAX_FUSES enabled, returning 1333MHz\n");</span><br><span> return TCK_1333MHZ;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> </span><br><span> rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);</span><br><span> </span><br><span> if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[get_mem_min_tck] p1\n");</span><br><span> /* read Capabilities A Register DMFC bits */</span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);</span><br><span> reg32 &= 0x7;</span><br><span>@@ -413,6 +448,7 @@</span><br><span> break;</span><br><span> }</span><br><span> } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[get_mem_min_tck] p2\n");</span><br><span> /* read Capabilities B Register DMFC bits */</span><br><span> reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B);</span><br><span> reg32 = (reg32 >> 4) & 0x7;</span><br><span>@@ -430,8 +466,10 @@</span><br><span> break;</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[get_mem_min_tck] p3, returning DEFAULT_TCK\n");</span><br><span> return DEFAULT_TCK;</span><br><span> } else {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[get_mem_min_tck] cfg->max_mem_clock_mhz=%d\n", cfg->max_mem_clock_mhz);</span><br><span> if (cfg->max_mem_clock_mhz >= 1066)</span><br><span> return TCK_1066MHZ;</span><br><span> else if (cfg->max_mem_clock_mhz >= 933)</span><br><span>diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>index 19dea2f..74a1210 100644</span><br><span>--- a/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c</span><br><span>@@ -533,7 +533,8 @@</span><br><span> static void dram_freq(ramctr_timing * ctrl)</span><br><span> {</span><br><span> if (ctrl->tCK > TCK_400MHZ) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk (BIOS_ERR, "DRAM frequency is under lowest supported "</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[dram_freq] forcing TCK_400MHZ, ctrl->tCK=%u\n", ctrl->tCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "DRAM frequency is under lowest supported "</span><br><span> "frequency (400 MHz). Increasing to 400 MHz as last resort");</span><br><span> ctrl->tCK = TCK_400MHZ;</span><br><span> }</span><br><span>@@ -641,6 +642,7 @@</span><br><span> </span><br><span> printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n",</span><br><span> fast_boot);</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "[try_init_dram_ddr3_ivy] tCK=%u\n", ctrl->tCK);</span><br><span> </span><br><span> if (!fast_boot) {</span><br><span> /* Find fastest common supported parameters */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26136">change 26136</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26136"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400 </div>
<div style="display:none"> Gerrit-Change-Number: 26136 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Anonymous Coward #1001983 </div>