[coreboot-gerrit] Change in coreboot[master]: vendorcode/amd/pi/00670F00: Control which procedure builds
Richard Spiegel (Code Review)
gerrit at coreboot.org
Mon May 7 16:54:34 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/26135
Change subject: vendorcode/amd/pi/00670F00: Control which procedure builds
......................................................................
vendorcode/amd/pi/00670F00: Control which procedure builds
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/Kconfig
M src/vendorcode/amd/pi/00670F00/Lib/amdlib.c
M src/vendorcode/amd/pi/00670F00/Makefile.inc
M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c
M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c
M src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c
7 files changed, 65 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26135/1
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index f544796..34b8159 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -393,4 +393,29 @@
return to S0. Otherwise the system will remain in S5 once power
is restored.
+config VENDORCODE_FULL_FCH_SUPPORT
+ def_bool n
+ help
+ This option determines if all files under
+ vendorcode/amd/pi/00670F00/Proc/Fch/Common will be compiled or only
+ selected procedures of file FchPeLib.c (minimum required).
+
+config VENDORCODE_FULL_AMDLIB_SUPPORT
+ def_bool n
+ help
+ This option determines if all procedures of file AmdLic.c will be
+ compiled or only selected procedures (minimum required).
+
+config VENDORCODE_FULL_AGESA_SUPPORT
+ def_bool n
+ help
+ This option determines if all procedures of file AGESA.c will be
+ compiled or only selected procedures (minimum required).
+
+config VENDORCODE_FULL_PSPBASELIB_SUPPORT
+ def_bool n
+ help
+ This option determines if all procedures of file PspBaseLib.c will
+ be compiled or only selected procedures (minimum required).
+
endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c
index 849d1a2..0784293 100644
--- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c
+++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c
@@ -274,6 +274,7 @@
}
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
AMDLIB_OPTIMIZE
VOID
LibAmdReadCpuReg (
@@ -388,6 +389,7 @@
return 0xFF; /* Error code indicating no bit found */
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
AMDLIB_OPTIMIZE
VOID
@@ -414,6 +416,7 @@
__writemsr (MsrAddress, *Value);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
AMDLIB_OPTIMIZE
void LibAmdCpuidRead (
IN UINT32 CpuidFcnAddress,
@@ -499,6 +502,7 @@
/* TODO: finit */
__asm__ volatile ("finit");
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
/*---------------------------------------------------------------------------------------*/
/**
* Read IO port
@@ -605,6 +609,7 @@
LibAmdIoWrite (AccessWidth, IoAddress, &Value, NULL);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
/*---------------------------------------------------------------------------------------*/
/**
* Poll IO register
@@ -637,6 +642,7 @@
LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL);
} while (TempData != (Value & TempMask));
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
/*---------------------------------------------------------------------------------------*/
/**
@@ -744,6 +750,7 @@
LibAmdMemWrite (AccessWidth, MemAddress, &Value, NULL);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
/*---------------------------------------------------------------------------------------*/
/**
* Poll Mmio
@@ -776,6 +783,7 @@
LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL);
} while (TempData != (Value & TempMask));
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
/*---------------------------------------------------------------------------------------*/
/**
@@ -913,6 +921,7 @@
LibAmdPciWrite (AccessWidth, PciAddress, &Value, NULL);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
/*---------------------------------------------------------------------------------------*/
/**
* Poll PCI config space register
@@ -945,6 +954,7 @@
LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL);
} while (TempData != (Value & TempMask));
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
/*---------------------------------------------------------------------------------------*/
/**
@@ -979,6 +989,7 @@
return MmioIsEnabled;
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
/*---------------------------------------------------------------------------------------*/
/**
* Read field of PCI config register.
@@ -1177,6 +1188,7 @@
*Dest++ = *SourcePtr++;
}
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
/*---------------------------------------------------------------------------------------*/
/**
@@ -1261,6 +1273,7 @@
return NULL;
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
/*---------------------------------------------------------------------------------------*/
/**
* Returns the package type mask for the processor
@@ -1282,6 +1295,7 @@
ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
return (UINT32) (1 << ProcessorPackageType);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
/*---------------------------------------------------------------------------------------*/
/**
@@ -1327,6 +1341,7 @@
}
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)
/*---------------------------------------------------------------------------------------*/
/**
* Returns the package type mask for the processor
@@ -1388,6 +1403,7 @@
CpuidRead (0x80000008, &Value);
return Value.ECX_Reg & 0xff;
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */
BOOLEAN
IdsErrorStop (
diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc
index a17d409..fe8ae15 100644
--- a/src/vendorcode/amd/pi/00670F00/Makefile.inc
+++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc
@@ -90,10 +90,14 @@
agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])
+ifeq ($(CONFIG_VENDORCODE_FULL_FCH_SUPPORT),y)
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])
+endif
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS])
ifeq ($(CONFIG_STONEYRIDGE_IMC_FWM),y)
agesa_raw_files += $(wildcard $(AGESA_ROOT)/Lib/imc/*.c)
+agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c
+agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c
endif
classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c
index 031027e..a8089bd 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c
@@ -77,6 +77,7 @@
}
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT)
/**< cimFchStall - Reserved */
VOID
CimFchStall (
@@ -670,3 +671,4 @@
ACPIMMIO8 (0xfed80280 + Index) |= 0;
}
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT) */
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c
index 46125584..9e583bf 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c
@@ -45,6 +45,7 @@
#include "cpuFamilyTranslation.h"
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT)
/*----------------------------------------------------------------------------------------*/
/**
* ProgramPciByteTable - Program PCI register by table (8 bits data)
@@ -211,6 +212,7 @@
}
}
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT) */
/**
* GetChipSysMode - Get Chip status
@@ -253,7 +255,7 @@
}
}
-
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT)
/**
* GetEfuseStatue - Get Efuse status
*
@@ -575,3 +577,4 @@
return TempData64;
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT) */
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
index 199c3ff..21f0f68 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
@@ -219,6 +219,7 @@
return (FALSE);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)
/**
* Get specific PSP Entry information, this routine will auto detect the processor for loading
* correct PSP Directory
@@ -325,6 +326,7 @@
PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \
(sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */
/**
Check if PSP device is present
@@ -347,6 +349,7 @@
return (FALSE);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)
/**
Check PSP Platform Seucre Enable State
HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode)
@@ -414,6 +417,7 @@
return (TRUE);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */
BOOLEAN
PspBarInitEarly ()
@@ -450,6 +454,7 @@
return (TRUE);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)
/**
Return the PspMMIO MMIO location
@@ -474,6 +479,7 @@
return (TRUE);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */
/**
Return the PspMMIO MMIO location
@@ -509,6 +515,7 @@
return (TRUE);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)
/**
* Acquire the Mutex for access PSP,X86 co-accessed register
* Call this routine before access SMIx98 & SMIxA8
@@ -675,4 +682,5 @@
return ((SleepType == 3) ? TRUE : FALSE);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c
index 4e6262d..e3f7fee 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c
@@ -157,6 +157,7 @@
return Dispatcher(LateParams);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT)
/**********************************************************************
* Interface call: AmdInitRecovery
**********************************************************************/
@@ -170,6 +171,7 @@
if (!Dispatcher) return AGESA_UNSUPPORTED;
return Dispatcher(RecoveryParams);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT) */
/**********************************************************************
* Interface call: AmdInitResume
@@ -241,6 +243,7 @@
return Dispatcher(AmdApExeParams);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT)
/**********************************************************************
* Interface service call: AmdGetApicId
**********************************************************************/
@@ -282,6 +285,7 @@
if (!Dispatcher) return AGESA_UNSUPPORTED;
return Dispatcher(AmdParamIdentify);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT) */
/**********************************************************************
* Interface service call: AmdReadEventLog
@@ -297,6 +301,7 @@
return Dispatcher(Event);
}
+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT)
/**********************************************************************
* Interface service call: AmdIdentifyDimm
**********************************************************************/
@@ -333,3 +338,4 @@
if (!Dispatcher) return AGESA_UNSUPPORTED;
return Dispatcher(AmdGetDataEye);
}
+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT) */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Gerrit-Change-Number: 26135
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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