<p>Richard Spiegel has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26135">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/amd/pi/00670F00: Control which procedure builds<br><br>Vendor code is compiled as a library, thus the whole library is included<br>into the final image. However, not all procedures are required, they are<br>there because original AGESA code had them. We cannot remove them, in order<br>to facilitate porting of fixed AGESA code. Therefor add #if throughout the<br>code to allow the control if unneeded procedures will be build.<br><br>BUG=b:78610011<br>TEST=Build and boot grunt; build kahlee and gardenia.<br><br>Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf<br>Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/vendorcode/amd/pi/00670F00/Lib/amdlib.c<br>M src/vendorcode/amd/pi/00670F00/Makefile.inc<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c<br>M src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c<br>M src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c<br>M src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c<br>7 files changed, 65 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26135/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig</span><br><span>index f544796..34b8159 100644</span><br><span>--- a/src/soc/amd/stoneyridge/Kconfig</span><br><span>+++ b/src/soc/amd/stoneyridge/Kconfig</span><br><span>@@ -393,4 +393,29 @@</span><br><span> return to S0. Otherwise the system will remain in S5 once power</span><br><span> is restored.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config VENDORCODE_FULL_FCH_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option determines if all files under</span><br><span style="color: hsl(120, 100%, 40%);">+ vendorcode/amd/pi/00670F00/Proc/Fch/Common will be compiled or only</span><br><span style="color: hsl(120, 100%, 40%);">+ selected procedures of file FchPeLib.c (minimum required).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VENDORCODE_FULL_AMDLIB_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option determines if all procedures of file AmdLic.c will be</span><br><span style="color: hsl(120, 100%, 40%);">+ compiled or only selected procedures (minimum required).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VENDORCODE_FULL_AGESA_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option determines if all procedures of file AGESA.c will be</span><br><span style="color: hsl(120, 100%, 40%);">+ compiled or only selected procedures (minimum required).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config VENDORCODE_FULL_PSPBASELIB_SUPPORT</span><br><span style="color: hsl(120, 100%, 40%);">+ def_bool n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ This option determines if all procedures of file PspBaseLib.c will</span><br><span style="color: hsl(120, 100%, 40%);">+ be compiled or only selected procedures (minimum required).</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c</span><br><span>index 849d1a2..0784293 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Lib/amdlib.c</span><br><span>@@ -274,6 +274,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> AMDLIB_OPTIMIZE</span><br><span> VOID</span><br><span> LibAmdReadCpuReg (</span><br><span>@@ -388,6 +389,7 @@</span><br><span> </span><br><span> return 0xFF; /* Error code indicating no bit found */</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> </span><br><span> AMDLIB_OPTIMIZE</span><br><span> VOID</span><br><span>@@ -414,6 +416,7 @@</span><br><span> __writemsr (MsrAddress, *Value);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> AMDLIB_OPTIMIZE</span><br><span> void LibAmdCpuidRead (</span><br><span> IN UINT32 CpuidFcnAddress,</span><br><span>@@ -499,6 +502,7 @@</span><br><span> /* TODO: finit */</span><br><span> __asm__ volatile ("finit");</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * Read IO port</span><br><span>@@ -605,6 +609,7 @@</span><br><span> LibAmdIoWrite (AccessWidth, IoAddress, &Value, NULL);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * Poll IO register</span><br><span>@@ -637,6 +642,7 @@</span><br><span> LibAmdIoRead (AccessWidth, IoAddress, &Value, NULL);</span><br><span> } while (TempData != (Value & TempMask));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span>@@ -744,6 +750,7 @@</span><br><span> LibAmdMemWrite (AccessWidth, MemAddress, &Value, NULL);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * Poll Mmio</span><br><span>@@ -776,6 +783,7 @@</span><br><span> LibAmdMemRead (AccessWidth, MemAddress, &Value, NULL);</span><br><span> } while (TempData != (Value & TempMask));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span>@@ -913,6 +921,7 @@</span><br><span> LibAmdPciWrite (AccessWidth, PciAddress, &Value, NULL);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * Poll PCI config space register</span><br><span>@@ -945,6 +954,7 @@</span><br><span> LibAmdPciRead (AccessWidth, PciAddress, &Value, NULL);</span><br><span> } while (TempData != (Value & TempMask));</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span>@@ -979,6 +989,7 @@</span><br><span> return MmioIsEnabled;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * Read field of PCI config register.</span><br><span>@@ -1177,6 +1188,7 @@</span><br><span> *Dest++ = *SourcePtr++;</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span>@@ -1261,6 +1273,7 @@</span><br><span> return NULL;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * Returns the package type mask for the processor</span><br><span>@@ -1282,6 +1295,7 @@</span><br><span> ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28</span><br><span> return (UINT32) (1 << ProcessorPackageType);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> </span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span>@@ -1327,6 +1341,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT)</span><br><span> /*---------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * Returns the package type mask for the processor</span><br><span>@@ -1388,6 +1403,7 @@</span><br><span> CpuidRead (0x80000008, &Value);</span><br><span> return Value.ECX_Reg & 0xff;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AMDLIB_SUPPORT) */</span><br><span> </span><br><span> BOOLEAN</span><br><span> IdsErrorStop (</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc</span><br><span>index a17d409..fe8ae15 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Makefile.inc</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc</span><br><span>@@ -90,10 +90,14 @@</span><br><span> </span><br><span> agesa_raw_files += $(wildcard $(AGESA_ROOT)/binaryPI/*.[cS])</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ifeq ($(CONFIG_VENDORCODE_FULL_FCH_SUPPORT),y)</span><br><span> agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS])</span><br><span style="color: hsl(120, 100%, 40%);">+endif</span><br><span> agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS])</span><br><span> ifeq ($(CONFIG_STONEYRIDGE_IMC_FWM),y)</span><br><span> agesa_raw_files += $(wildcard $(AGESA_ROOT)/Lib/imc/*.c)</span><br><span style="color: hsl(120, 100%, 40%);">+agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchLib.c</span><br><span style="color: hsl(120, 100%, 40%);">+agesa_raw_files += $(AGESA_ROOT)/Proc/Fch/Common/FchPeLib.c</span><br><span> endif</span><br><span> </span><br><span> classes-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += libagesa</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c</span><br><span>index 031027e..a8089bd 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c</span><br><span>@@ -77,6 +77,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT)</span><br><span> /**< cimFchStall - Reserved */</span><br><span> VOID</span><br><span> CimFchStall (</span><br><span>@@ -670,3 +671,4 @@</span><br><span> ACPIMMIO8 (0xfed80280 + Index) |= 0;</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT) */</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c</span><br><span>index 46125584..9e583bf 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c</span><br><span>@@ -45,6 +45,7 @@</span><br><span> #include "cpuFamilyTranslation.h"</span><br><span> #define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT)</span><br><span> /*----------------------------------------------------------------------------------------*/</span><br><span> /**</span><br><span> * ProgramPciByteTable - Program PCI register by table (8 bits data)</span><br><span>@@ -211,6 +212,7 @@</span><br><span> }</span><br><span> }</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT) */</span><br><span> </span><br><span> /**</span><br><span> * GetChipSysMode - Get Chip status</span><br><span>@@ -253,7 +255,7 @@</span><br><span> }</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT)</span><br><span> /**</span><br><span> * GetEfuseStatue - Get Efuse status</span><br><span> *</span><br><span>@@ -575,3 +577,4 @@</span><br><span> </span><br><span> return TempData64;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_FCH_SUPPORT) */</span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c</span><br><span>index 199c3ff..21f0f68 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c</span><br><span>@@ -219,6 +219,7 @@</span><br><span> return (FALSE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)</span><br><span> /**</span><br><span> * Get specific PSP Entry information, this routine will auto detect the processor for loading</span><br><span> * correct PSP Directory</span><br><span>@@ -325,6 +326,7 @@</span><br><span> PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \</span><br><span> (sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */</span><br><span> </span><br><span> /**</span><br><span> Check if PSP device is present</span><br><span>@@ -347,6 +349,7 @@</span><br><span> return (FALSE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)</span><br><span> /**</span><br><span> Check PSP Platform Seucre Enable State</span><br><span> HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode)</span><br><span>@@ -414,6 +417,7 @@</span><br><span> </span><br><span> return (TRUE);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */</span><br><span> </span><br><span> BOOLEAN</span><br><span> PspBarInitEarly ()</span><br><span>@@ -450,6 +454,7 @@</span><br><span> return (TRUE);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)</span><br><span> /**</span><br><span> Return the PspMMIO MMIO location</span><br><span> </span><br><span>@@ -474,6 +479,7 @@</span><br><span> </span><br><span> return (TRUE);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */</span><br><span> </span><br><span> /**</span><br><span> Return the PspMMIO MMIO location</span><br><span>@@ -509,6 +515,7 @@</span><br><span> </span><br><span> return (TRUE);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT)</span><br><span> /**</span><br><span> * Acquire the Mutex for access PSP,X86 co-accessed register</span><br><span> * Call this routine before access SMIx98 & SMIxA8</span><br><span>@@ -675,4 +682,5 @@</span><br><span> </span><br><span> return ((SleepType == 3) ? TRUE : FALSE);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_PSPBASELIB_SUPPORT) */</span><br><span> </span><br><span>diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c</span><br><span>index 4e6262d..e3f7fee 100644</span><br><span>--- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c</span><br><span>+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c</span><br><span>@@ -157,6 +157,7 @@</span><br><span> return Dispatcher(LateParams);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT)</span><br><span> /**********************************************************************</span><br><span> * Interface call: AmdInitRecovery</span><br><span> **********************************************************************/</span><br><span>@@ -170,6 +171,7 @@</span><br><span> if (!Dispatcher) return AGESA_UNSUPPORTED;</span><br><span> return Dispatcher(RecoveryParams);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT) */</span><br><span> </span><br><span> /**********************************************************************</span><br><span> * Interface call: AmdInitResume</span><br><span>@@ -241,6 +243,7 @@</span><br><span> return Dispatcher(AmdApExeParams);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT)</span><br><span> /**********************************************************************</span><br><span> * Interface service call: AmdGetApicId</span><br><span> **********************************************************************/</span><br><span>@@ -282,6 +285,7 @@</span><br><span> if (!Dispatcher) return AGESA_UNSUPPORTED;</span><br><span> return Dispatcher(AmdParamIdentify);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT) */</span><br><span> </span><br><span> /**********************************************************************</span><br><span> * Interface service call: AmdReadEventLog</span><br><span>@@ -297,6 +301,7 @@</span><br><span> return Dispatcher(Event);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT)</span><br><span> /**********************************************************************</span><br><span> * Interface service call: AmdIdentifyDimm</span><br><span> **********************************************************************/</span><br><span>@@ -333,3 +338,4 @@</span><br><span> if (!Dispatcher) return AGESA_UNSUPPORTED;</span><br><span> return Dispatcher(AmdGetDataEye);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_AGESA_SUPPORT) */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26135">change 26135</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26135"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf </div>
<div style="display:none"> Gerrit-Change-Number: 26135 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>