[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Move cse common functions into block/cse
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon May 7 14:47:59 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26133
Change subject: soc/intel/common/block: Move cse common functions into block/cse
......................................................................
soc/intel/common/block: Move cse common functions into block/cse
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/cse.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
6 files changed, 52 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/26133/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 2f7e9c2..662f29d 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -48,6 +48,7 @@
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_CSE
+ select SOC_INTEL_COMMON_BLOCK_CSE_DISABLE_IN_SMM
select SOC_INTEL_COMMON_BLOCK_DSP
select SOC_INTEL_COMMON_BLOCK_EBDA
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 05b7a7a..1774bc3 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -19,55 +19,17 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/fast_spi.h>
-#include <intelblocks/p2sb.h>
-#include <intelblocks/pcr.h>
+#include <intelblocks/cse.h>
#include <intelblocks/smihandler.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
#include <soc/pm.h>
-#define CSME0_FBE 0xf
-#define CSME0_BAR 0x0
-#define CSME0_FID 0xb0
-
const struct smm_save_state_ops *get_smm_save_state_ops(void)
{
return &em64t101_smm_ops;
}
-static void pch_disable_heci(void)
-{
- device_t dev = PCH_DEV_P2SB;
- struct pcr_sbi_msg msg = {
- .pid = PID_CSME0,
- .offset = 0,
- .opcode = PCR_WRITE,
- .is_posted = false,
- .fast_byte_enable = CSME0_FBE,
- .bar = CSME0_BAR,
- .fid = CSME0_FID
- };
- /* Bit 0: Set to make HECI#1 Function disable */
- uint32_t data32 = 1;
- uint8_t response;
- int status;
-
- /* unhide p2sb device */
- p2sb_unhide();
-
- /* Send SBI command to make HECI#1 function disable */
- status = pcr_execute_sideband_msg(&msg, &data32, &response);
- if (status && response)
- printk(BIOS_ERR, "Fail to make CSME function disable\n");
-
- /* Ensure to Lock SBI interface after this command */
- p2sb_disable_sideband_access(dev);
-
- /* hide p2sb device */
- p2sb_hide();
-}
-
/*
* Specific SOC SMI handler during ramstage finalize phase
*
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 321d34c..411ee2b 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -4,3 +4,9 @@
help
Driver for communication with Converged Security Engine (CSE)
over Host Embedded Controller Interface (HECI)
+
+config SOC_INTEL_COMMON_BLOCK_CSE_DISABLE_IN_SMM
+ bool
+ default n
+ help
+ Use this config to make to make CSME function disable in SMM mode
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc
index 376f00f..9228ec0 100644
--- a/src/soc/intel/common/block/cse/Makefile.inc
+++ b/src/soc/intel/common/block/cse/Makefile.inc
@@ -1,3 +1,4 @@
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 4991db6..aa4cf13 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -22,8 +22,11 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <intelblocks/cse.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/pcr.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
#include <string.h>
#include <timer.h>
@@ -67,6 +70,9 @@
#define MEI_HDR_CSE_ADDR_START 0
#define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
+#define CSME0_FBE 0xf
+#define CSME0_BAR 0x0
+#define CSME0_FID 0xb0
struct cse_device {
uintptr_t sec_bar;
@@ -486,6 +492,41 @@
return 0;
}
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE_DISABLE_IN_SMM)
+/* Disable HECI using Sideband interface communication */
+void pch_disable_heci(void)
+{
+ device_t dev = PCH_DEV_P2SB;
+ struct pcr_sbi_msg msg = {
+ .pid = PID_CSME0,
+ .offset = 0,
+ .opcode = PCR_WRITE,
+ .is_posted = false,
+ .fast_byte_enable = CSME0_FBE,
+ .bar = CSME0_BAR,
+ .fid = CSME0_FID
+ };
+ /* Bit 0: Set to make HECI#1 Function disable */
+ uint32_t data32 = 1;
+ uint8_t response;
+ int status;
+
+ /* unhide p2sb device */
+ p2sb_unhide();
+
+ /* Send SBI command to make HECI#1 function disable */
+ status = pcr_execute_sideband_msg(&msg, &data32, &response);
+ if (status && response)
+ printk(BIOS_ERR, "Fail to make CSME function disable\n");
+
+ /* Ensure to Lock SBI interface after this command */
+ p2sb_disable_sideband_access(dev);
+
+ /* hide p2sb device */
+ p2sb_hide();
+}
+#endif
+
#if ENV_RAMSTAGE
static void update_sec_bar(struct device *dev)
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index d7c4d9f..b76081b 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -43,6 +43,8 @@
* Returns 0 on failure a 1 on success.
*/
int heci_reset(void);
+/* Disable HECI using Sideband interface communication */
+void pch_disable_heci(void);
#define BIOS_HOST_ADDR 0x00
#define HECI_MKHI_ADDR 0x07
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Gerrit-Change-Number: 26133
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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