<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26133">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Move cse common functions into block/cse<br><br>This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving<br>common soc code into common/block/cse.<br><br>BUG=b:78109109<br>BRANCH=none<br>TEST=Build and boot KBL/CNL/APL platform.<br><br>Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/smihandler.c<br>M src/soc/intel/common/block/cse/Kconfig<br>M src/soc/intel/common/block/cse/Makefile.inc<br>M src/soc/intel/common/block/cse/cse.c<br>M src/soc/intel/common/block/include/intelblocks/cse.h<br>6 files changed, 52 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/26133/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 2f7e9c2..662f29d 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -48,6 +48,7 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT</span><br><span> select SOC_INTEL_COMMON_BLOCK_CSE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_CSE_DISABLE_IN_SMM</span><br><span> select SOC_INTEL_COMMON_BLOCK_DSP</span><br><span> select SOC_INTEL_COMMON_BLOCK_EBDA</span><br><span> select SOC_INTEL_COMMON_BLOCK_FAST_SPI</span><br><span>diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c</span><br><span>index 05b7a7a..1774bc3 100644</span><br><span>--- a/src/soc/intel/cannonlake/smihandler.c</span><br><span>+++ b/src/soc/intel/cannonlake/smihandler.c</span><br><span>@@ -19,55 +19,17 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/p2sb.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/cse.h></span><br><span> #include <intelblocks/smihandler.h></span><br><span> #include <soc/p2sb.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pcr_ids.h></span><br><span> #include <soc/pm.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define CSME0_FBE 0xf</span><br><span style="color: hsl(0, 100%, 40%);">-#define CSME0_BAR 0x0</span><br><span style="color: hsl(0, 100%, 40%);">-#define CSME0_FID 0xb0</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> const struct smm_save_state_ops *get_smm_save_state_ops(void)</span><br><span> {</span><br><span> return &em64t101_smm_ops;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_disable_heci(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- device_t dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(0, 100%, 40%);">- struct pcr_sbi_msg msg = {</span><br><span style="color: hsl(0, 100%, 40%);">- .pid = PID_CSME0,</span><br><span style="color: hsl(0, 100%, 40%);">- .offset = 0,</span><br><span style="color: hsl(0, 100%, 40%);">- .opcode = PCR_WRITE,</span><br><span style="color: hsl(0, 100%, 40%);">- .is_posted = false,</span><br><span style="color: hsl(0, 100%, 40%);">- .fast_byte_enable = CSME0_FBE,</span><br><span style="color: hsl(0, 100%, 40%);">- .bar = CSME0_BAR,</span><br><span style="color: hsl(0, 100%, 40%);">- .fid = CSME0_FID</span><br><span style="color: hsl(0, 100%, 40%);">- };</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bit 0: Set to make HECI#1 Function disable */</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t data32 = 1;</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t response;</span><br><span style="color: hsl(0, 100%, 40%);">- int status;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* unhide p2sb device */</span><br><span style="color: hsl(0, 100%, 40%);">- p2sb_unhide();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Send SBI command to make HECI#1 function disable */</span><br><span style="color: hsl(0, 100%, 40%);">- status = pcr_execute_sideband_msg(&msg, &data32, &response);</span><br><span style="color: hsl(0, 100%, 40%);">- if (status && response)</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Fail to make CSME function disable\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Ensure to Lock SBI interface after this command */</span><br><span style="color: hsl(0, 100%, 40%);">- p2sb_disable_sideband_access(dev);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* hide p2sb device */</span><br><span style="color: hsl(0, 100%, 40%);">- p2sb_hide();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /*</span><br><span> * Specific SOC SMI handler during ramstage finalize phase</span><br><span> *</span><br><span>diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig</span><br><span>index 321d34c..411ee2b 100644</span><br><span>--- a/src/soc/intel/common/block/cse/Kconfig</span><br><span>+++ b/src/soc/intel/common/block/cse/Kconfig</span><br><span>@@ -4,3 +4,9 @@</span><br><span> help</span><br><span> Driver for communication with Converged Security Engine (CSE)</span><br><span> over Host Embedded Controller Interface (HECI)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BLOCK_CSE_DISABLE_IN_SMM</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ Use this config to make to make CSME function disable in SMM mode</span><br><span>diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc</span><br><span>index 376f00f..9228ec0 100644</span><br><span>--- a/src/soc/intel/common/block/cse/Makefile.inc</span><br><span>+++ b/src/soc/intel/common/block/cse/Makefile.inc</span><br><span>@@ -1,3 +1,4 @@</span><br><span> bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c</span><br><span> romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c</span><br><span> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c</span><br><span>diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c</span><br><span>index 4991db6..aa4cf13 100644</span><br><span>--- a/src/soc/intel/common/block/cse/cse.c</span><br><span>+++ b/src/soc/intel/common/block/cse/cse.c</span><br><span>@@ -22,8 +22,11 @@</span><br><span> #include <device/pci_ids.h></span><br><span> #include <device/pci_ops.h></span><br><span> #include <intelblocks/cse.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span> #include <soc/iomap.h></span><br><span> #include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span> #include <string.h></span><br><span> #include <timer.h></span><br><span> </span><br><span>@@ -67,6 +70,9 @@</span><br><span> #define MEI_HDR_CSE_ADDR_START 0</span><br><span> #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_FBE 0xf</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_BAR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CSME0_FID 0xb0</span><br><span> </span><br><span> struct cse_device {</span><br><span> uintptr_t sec_bar;</span><br><span>@@ -486,6 +492,41 @@</span><br><span> return 0;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE_DISABLE_IN_SMM)</span><br><span style="color: hsl(120, 100%, 40%);">+/* Disable HECI using Sideband interface communication */</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_disable_heci(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ device_t dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct pcr_sbi_msg msg = {</span><br><span style="color: hsl(120, 100%, 40%);">+ .pid = PID_CSME0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .offset = 0,</span><br><span style="color: hsl(120, 100%, 40%);">+ .opcode = PCR_WRITE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .is_posted = false,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fast_byte_enable = CSME0_FBE,</span><br><span style="color: hsl(120, 100%, 40%);">+ .bar = CSME0_BAR,</span><br><span style="color: hsl(120, 100%, 40%);">+ .fid = CSME0_FID</span><br><span style="color: hsl(120, 100%, 40%);">+ };</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bit 0: Set to make HECI#1 Function disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t data32 = 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t response;</span><br><span style="color: hsl(120, 100%, 40%);">+ int status;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* unhide p2sb device */</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_unhide();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Send SBI command to make HECI#1 function disable */</span><br><span style="color: hsl(120, 100%, 40%);">+ status = pcr_execute_sideband_msg(&msg, &data32, &response);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (status && response)</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "Fail to make CSME function disable\n");</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Ensure to Lock SBI interface after this command */</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_disable_sideband_access(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* hide p2sb device */</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_hide();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #if ENV_RAMSTAGE</span><br><span> </span><br><span> static void update_sec_bar(struct device *dev)</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h</span><br><span>index d7c4d9f..b76081b 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/cse.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/cse.h</span><br><span>@@ -43,6 +43,8 @@</span><br><span> * Returns 0 on failure a 1 on success.</span><br><span> */</span><br><span> int heci_reset(void);</span><br><span style="color: hsl(120, 100%, 40%);">+/* Disable HECI using Sideband interface communication */</span><br><span style="color: hsl(120, 100%, 40%);">+void pch_disable_heci(void);</span><br><span> </span><br><span> #define BIOS_HOST_ADDR 0x00</span><br><span> #define HECI_MKHI_ADDR 0x07</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26133">change 26133</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26133"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 </div>
<div style="display:none"> Gerrit-Change-Number: 26133 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>