[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Move p2sb common functions into block/p2sb
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon May 7 14:15:36 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/26132
Change subject: soc/intel/common/block: Move p2sb common functions into block/p2sb
......................................................................
soc/intel/common/block: Move p2sb common functions into block/p2sb
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/p2sb.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
A src/soc/intel/apollolake/include/soc/p2sb.h
M src/soc/intel/cannonlake/include/soc/p2sb.h
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/include/intelblocks/p2sb.h
M src/soc/intel/common/block/p2sb/Makefile.inc
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/skylake/acpi.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/p2sb.h
9 files changed, 65 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/26132/1
diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h
new file mode 100644
index 0000000..5bf8b2c
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/p2sb.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_P2SB_H_
+#define _SOC_P2SB_H_
+
+#define PCH_P2SB_EPMASK0 0xB0
+
+#endif /* _SOC_P2SB_H_ */
diff --git a/src/soc/intel/cannonlake/include/soc/p2sb.h b/src/soc/intel/cannonlake/include/soc/p2sb.h
index 8b2e437..73a5053 100644
--- a/src/soc/intel/cannonlake/include/soc/p2sb.h
+++ b/src/soc/intel/cannonlake/include/soc/p2sb.h
@@ -20,8 +20,5 @@
#define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0x220
-#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
-
-#define PCH_P2SB_E0 0xE0
#endif
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index ba010aa..05b7a7a 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/pci_def.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <intelblocks/smihandler.h>
#include <soc/p2sb.h>
@@ -35,29 +36,6 @@
return &em64t101_smm_ops;
}
-static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)
-{
- uint32_t reg32;
-
- reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));
- pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);
-}
-
-static void disable_sideband_access(device_t dev)
-{
- u8 reg8;
- uint32_t mask;
-
- /* Remove the host accessing right to PSF register range. */
- /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */
- mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
- pch_configure_endpoints(dev, 5, mask);
-
- /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */
- reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);
- pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));
-}
-
static void pch_disable_heci(void)
{
device_t dev = PCH_DEV_P2SB;
@@ -76,7 +54,7 @@
int status;
/* unhide p2sb device */
- pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);
+ p2sb_unhide();
/* Send SBI command to make HECI#1 function disable */
status = pcr_execute_sideband_msg(&msg, &data32, &response);
@@ -84,10 +62,10 @@
printk(BIOS_ERR, "Fail to make CSME function disable\n");
/* Ensure to Lock SBI interface after this command */
- disable_sideband_access(dev);
+ p2sb_disable_sideband_access(dev);
/* hide p2sb device */
- pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);
+ p2sb_hide();
}
/*
diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h
index 8139a69..ba4f978 100644
--- a/src/soc/intel/common/block/include/intelblocks/p2sb.h
+++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h
@@ -16,7 +16,13 @@
#ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H
#define SOC_INTEL_COMMON_BLOCK_P2SB_H
+#include <soc/p2sb.h>
+
+#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
+#define PCH_P2SB_E0 0xe0
+
void p2sb_unhide(void);
void p2sb_hide(void);
+void p2sb_disable_sideband_access(device_t dev);
#endif /* SOC_INTEL_COMMON_BLOCK_P2SB_H */
diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc
index d78714b..bf5ad08 100644
--- a/src/soc/intel/common/block/p2sb/Makefile.inc
+++ b/src/soc/intel/common/block/p2sb/Makefile.inc
@@ -1 +1,2 @@
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 6a9bd34..1cb1966 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -23,18 +23,21 @@
#include <soc/pci_devs.h>
#include <intelblocks/p2sb.h>
-#define P2SB_E0 0xe0
#define HIDE_BIT (1 << 0)
static void p2sb_set_hide_bit(int hide)
{
+#if defined(__SIMPLE_DEVICE__)
+ int devfn = PCH_DEVFN_P2SB;
+ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
+#else
struct device *dev;
- const uint16_t reg = P2SB_E0 + 1;
+ dev = PCH_DEV_P2SB;
+#endif
+ const uint16_t reg = PCH_P2SB_E0 + 1;
const uint8_t mask = HIDE_BIT;
uint8_t val;
- dev = PCH_DEV_P2SB;
-
val = pci_read_config8(dev, reg);
val &= ~mask;
if (hide)
@@ -52,6 +55,30 @@
p2sb_set_hide_bit(1);
}
+static void p2sb_configure_endpoints(device_t dev, int epmask_id,
+ uint32_t mask)
+{
+ uint32_t reg32;
+
+ reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));
+ pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);
+}
+
+void p2sb_disable_sideband_access(device_t dev)
+{
+ u8 reg8;
+ uint32_t mask;
+
+ /* Remove the host accessing right to PSF register range. */
+ /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */
+ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
+ p2sb_configure_endpoints(dev, 5, mask);
+
+ /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */
+ reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);
+ pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));
+}
+
static void read_resources(struct device *dev)
{
/*
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 914b9d5..e42b9c7 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -33,6 +33,7 @@
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/lpc_lib.h>
+#include <intelblocks/p2sb.h>
#include <intelblocks/sgx.h>
#include <intelblocks/uart.h>
#include <intelblocks/systemagent.h>
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 25b7484..1f34225 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -22,6 +22,7 @@
#include <cpu/x86/smm.h>
#include <device/pci.h>
#include <intelblocks/lpc_lib.h>
+#include <intelblocks/p2sb.h>
#include <intelblocks/pcr.h>
#include <reg_script.h>
#include <spi-generic.h>
diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h
index 09e73fc..8d7c11a 100644
--- a/src/soc/intel/skylake/include/soc/p2sb.h
+++ b/src/soc/intel/skylake/include/soc/p2sb.h
@@ -23,9 +23,7 @@
#define PCH_P2SB_HBDF 0x70
#define PCH_P2SB_EPMASK0 0xB0
-#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
-#define PCH_P2SB_E0 0xE0
#define PCH_PWRM_ACPI_TMR_CTL 0xFC
#endif /* _SOC_P2SB_H_ */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Gerrit-Change-Number: 26132
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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