<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26132">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Move p2sb common functions into block/p2sb<br><br>This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving<br>common soc code into common/block/p2sb.<br><br>BUG=b:78109109<br>BRANCH=none<br>TEST=Build and boot KBL/CNL/APL platform.<br><br>Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>A src/soc/intel/apollolake/include/soc/p2sb.h<br>M src/soc/intel/cannonlake/include/soc/p2sb.h<br>M src/soc/intel/cannonlake/smihandler.c<br>M src/soc/intel/common/block/include/intelblocks/p2sb.h<br>M src/soc/intel/common/block/p2sb/Makefile.inc<br>M src/soc/intel/common/block/p2sb/p2sb.c<br>M src/soc/intel/skylake/acpi.c<br>M src/soc/intel/skylake/finalize.c<br>M src/soc/intel/skylake/include/soc/p2sb.h<br>9 files changed, 65 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/26132/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h</span><br><span>new file mode 100644</span><br><span>index 0000000..5bf8b2c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/apollolake/include/soc/p2sb.h</span><br><span>@@ -0,0 +1,21 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _SOC_P2SB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+#define _SOC_P2SB_H_</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_P2SB_EPMASK0 0xB0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _SOC_P2SB_H_ */</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/p2sb.h b/src/soc/intel/cannonlake/include/soc/p2sb.h</span><br><span>index 8b2e437..73a5053 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/p2sb.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/p2sb.h</span><br><span>@@ -20,8 +20,5 @@</span><br><span> #define HPTC_ADDR_ENABLE_BIT (1 << 7)</span><br><span> </span><br><span> #define PCH_P2SB_EPMASK0 0x220</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_P2SB_E0 0xE0</span><br><span> </span><br><span> #endif</span><br><span>diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c</span><br><span>index ba010aa..05b7a7a 100644</span><br><span>--- a/src/soc/intel/cannonlake/smihandler.c</span><br><span>+++ b/src/soc/intel/cannonlake/smihandler.c</span><br><span>@@ -19,6 +19,7 @@</span><br><span> #include <console/console.h></span><br><span> #include <device/pci_def.h></span><br><span> #include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/p2sb.h></span><br><span> #include <intelblocks/pcr.h></span><br><span> #include <intelblocks/smihandler.h></span><br><span> #include <soc/p2sb.h></span><br><span>@@ -35,29 +36,6 @@</span><br><span> return &em64t101_smm_ops;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static void pch_configure_endpoints(device_t dev, int epmask_id, uint32_t mask)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void disable_sideband_access(device_t dev)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t mask;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Remove the host accessing right to PSF register range. */</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */</span><br><span style="color: hsl(0, 100%, 40%);">- mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);</span><br><span style="color: hsl(0, 100%, 40%);">- pch_configure_endpoints(dev, 5, mask);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> static void pch_disable_heci(void)</span><br><span> {</span><br><span> device_t dev = PCH_DEV_P2SB;</span><br><span>@@ -76,7 +54,7 @@</span><br><span> int status;</span><br><span> </span><br><span> /* unhide p2sb device */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCH_P2SB_E0 + 1, 0);</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_unhide();</span><br><span> </span><br><span> /* Send SBI command to make HECI#1 function disable */</span><br><span> status = pcr_execute_sideband_msg(&msg, &data32, &response);</span><br><span>@@ -84,10 +62,10 @@</span><br><span> printk(BIOS_ERR, "Fail to make CSME function disable\n");</span><br><span> </span><br><span> /* Ensure to Lock SBI interface after this command */</span><br><span style="color: hsl(0, 100%, 40%);">- disable_sideband_access(dev);</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_disable_sideband_access(dev);</span><br><span> </span><br><span> /* hide p2sb device */</span><br><span style="color: hsl(0, 100%, 40%);">- pci_write_config8(dev, PCH_P2SB_E0 + 1, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_hide();</span><br><span> }</span><br><span> </span><br><span> /*</span><br><span>diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h</span><br><span>index 8139a69..ba4f978 100644</span><br><span>--- a/src/soc/intel/common/block/include/intelblocks/p2sb.h</span><br><span>+++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h</span><br><span>@@ -16,7 +16,13 @@</span><br><span> #ifndef SOC_INTEL_COMMON_BLOCK_P2SB_H</span><br><span> #define SOC_INTEL_COMMON_BLOCK_P2SB_H</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/p2sb.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCH_P2SB_E0 0xe0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void p2sb_unhide(void);</span><br><span> void p2sb_hide(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void p2sb_disable_sideband_access(device_t dev);</span><br><span> </span><br><span> #endif /* SOC_INTEL_COMMON_BLOCK_P2SB_H */</span><br><span>diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc</span><br><span>index d78714b..bf5ad08 100644</span><br><span>--- a/src/soc/intel/common/block/p2sb/Makefile.inc</span><br><span>+++ b/src/soc/intel/common/block/p2sb/Makefile.inc</span><br><span>@@ -1 +1,2 @@</span><br><span> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c</span><br><span style="color: hsl(120, 100%, 40%);">+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c</span><br><span>diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c</span><br><span>index 6a9bd34..1cb1966 100644</span><br><span>--- a/src/soc/intel/common/block/p2sb/p2sb.c</span><br><span>+++ b/src/soc/intel/common/block/p2sb/p2sb.c</span><br><span>@@ -23,18 +23,21 @@</span><br><span> #include <soc/pci_devs.h></span><br><span> #include <intelblocks/p2sb.h></span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define P2SB_E0 0xe0</span><br><span> #define HIDE_BIT (1 << 0)</span><br><span> </span><br><span> static void p2sb_set_hide_bit(int hide)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+#if defined(__SIMPLE_DEVICE__)</span><br><span style="color: hsl(120, 100%, 40%);">+ int devfn = PCH_DEVFN_P2SB;</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span> struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">- const uint16_t reg = P2SB_E0 + 1;</span><br><span style="color: hsl(120, 100%, 40%);">+ dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+ const uint16_t reg = PCH_P2SB_E0 + 1;</span><br><span> const uint8_t mask = HIDE_BIT;</span><br><span> uint8_t val;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- dev = PCH_DEV_P2SB;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> val = pci_read_config8(dev, reg);</span><br><span> val &= ~mask;</span><br><span> if (hide)</span><br><span>@@ -52,6 +55,30 @@</span><br><span> p2sb_set_hide_bit(1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void p2sb_configure_endpoints(device_t dev, int epmask_id,</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mask)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = pci_read_config32(dev, PCH_P2SB_EPMASK(epmask_id));</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config32(dev, PCH_P2SB_EPMASK(epmask_id), reg32 | mask);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void p2sb_disable_sideband_access(device_t dev)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t mask;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Remove the host accessing right to PSF register range. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to [1, 1, 1, 1] */</span><br><span style="color: hsl(120, 100%, 40%);">+ mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);</span><br><span style="color: hsl(120, 100%, 40%);">+ p2sb_configure_endpoints(dev, 5, mask);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1. */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = pci_read_config8(dev, PCH_P2SB_E0 + 2);</span><br><span style="color: hsl(120, 100%, 40%);">+ pci_write_config8(dev, PCH_P2SB_E0 + 2, reg8 | (1 << 1));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void read_resources(struct device *dev)</span><br><span> {</span><br><span> /*</span><br><span>diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c</span><br><span>index 914b9d5..e42b9c7 100644</span><br><span>--- a/src/soc/intel/skylake/acpi.c</span><br><span>+++ b/src/soc/intel/skylake/acpi.c</span><br><span>@@ -33,6 +33,7 @@</span><br><span> #include <ec/google/chromeec/ec.h></span><br><span> #include <intelblocks/cpulib.h></span><br><span> #include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/p2sb.h></span><br><span> #include <intelblocks/sgx.h></span><br><span> #include <intelblocks/uart.h></span><br><span> #include <intelblocks/systemagent.h></span><br><span>diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c</span><br><span>index 25b7484..1f34225 100644</span><br><span>--- a/src/soc/intel/skylake/finalize.c</span><br><span>+++ b/src/soc/intel/skylake/finalize.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <cpu/x86/smm.h></span><br><span> #include <device/pci.h></span><br><span> #include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/p2sb.h></span><br><span> #include <intelblocks/pcr.h></span><br><span> #include <reg_script.h></span><br><span> #include <spi-generic.h></span><br><span>diff --git a/src/soc/intel/skylake/include/soc/p2sb.h b/src/soc/intel/skylake/include/soc/p2sb.h</span><br><span>index 09e73fc..8d7c11a 100644</span><br><span>--- a/src/soc/intel/skylake/include/soc/p2sb.h</span><br><span>+++ b/src/soc/intel/skylake/include/soc/p2sb.h</span><br><span>@@ -23,9 +23,7 @@</span><br><span> #define PCH_P2SB_HBDF 0x70</span><br><span> </span><br><span> #define PCH_P2SB_EPMASK0 0xB0</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH_P2SB_E0 0xE0</span><br><span> #define PCH_PWRM_ACPI_TMR_CTL 0xFC</span><br><span> </span><br><span> #endif /* _SOC_P2SB_H_ */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26132">change 26132</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a </div>
<div style="display:none"> Gerrit-Change-Number: 26132 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>