[coreboot-gerrit] Change in coreboot[master]: intel/fsp/fsp2_0: Fix FSP 2.0 headers to match github version

[Youness Alaoui (Code Review)]

Hello Matt DeVillier,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/26108

to review the following change.


Change subject: intel/fsp/fsp2_0: Fix FSP 2.0 headers to match github version
......................................................................

intel/fsp/fsp2_0: Fix FSP 2.0 headers to match github version

The current FSP 2.0 headers do not match the headers from the official
FSP 2.0 image that was released on github [1].

The SpiFlashCfgLockDown, PcieRpClkSrcNumber and IslVrCmd fields in the
FspsUpd structure do not exist in the github version, but they are kept
here because they are used by coreboot and are not causing problems when
set as it only changed UnusedUpdSpace in the github UPD.

The MEMORY_INFO_DATA_HOB structure has its EfiHobGuidType field removed
because hob_header_to_extension_hob in drivers/intel/fsp2_0/
called by fsp_find_extension_hob_by_guid will actually remove it before
returning the structure pointer.

[1] https://github.com/IntelFsp/FSP/tree/Kabylake/KabylakeFspBinPkg

Change-Id: I233bf7cf6f62e9e1b389d42a09461717a3285f0f
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
---
M src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
1 file changed, 1 insertion(+), 11 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/26108/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
index 248b4d5..629cee4 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
@@ -170,13 +170,6 @@
   UINT16 tWTR_S;    ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
 } MRC_CH_TIMING;
 
-typedef struct {
-  UINT8 SG;         ///< Number of tCK cycles between transactions in the same bank group.
-  UINT8 DG;         ///< Number of tCK cycles between transactions when switching bank groups.
-  UINT8 DR;         ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
-  UINT8 DD;         ///< Number of tCK cycles between transactions when switching between DIMMs.
-} MRC_TA_TIMING;
-
 ///
 /// Memory SMBIOS & OC Memory Data Hob
 ///
@@ -207,10 +200,6 @@
   UINT8             RevisionId;              ///< The PCI revision id of this memory controller.
   UINT8             ChannelCount;            ///< Number of valid channels that exist on the controller.
   CHANNEL_INFO      ChannelInfo[MAX_CH];     ///< The following are channel level definitions.
-  MRC_TA_TIMING     tRd2Rd;                  ///< Read-to-Read   Turn Around Timings
-  MRC_TA_TIMING     tRd2Wr;                  ///< Read-to-Write  Turn Around Timings
-  MRC_TA_TIMING     tWr2Rd;                  ///< Write-to-Read  Turn Around Timings
-  MRC_TA_TIMING     tWr2Wr;                  ///< Write-to-Write Turn Around Timings
 } CONTROLLER_INFO;
 
 typedef struct {
@@ -228,6 +217,7 @@
   UINT8             ErrorCorrectionType;
 
   SiMrcVersion      Version;
+  UINT32            FreqMax;
   BOOLEAN           EccSupport;
   UINT8             MemoryProfile;
   UINT32            TotalPhysicalMemorySize;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I233bf7cf6f62e9e1b389d42a09461717a3285f0f
Gerrit-Change-Number: 26108
Gerrit-PatchSet: 1
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>
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