<p>Youness Alaoui would like Matt DeVillier to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/26108">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/fsp/fsp2_0: Fix FSP 2.0 headers to match github version<br><br>The current FSP 2.0 headers do not match the headers from the official<br>FSP 2.0 image that was released on github [1].<br><br>The SpiFlashCfgLockDown, PcieRpClkSrcNumber and IslVrCmd fields in the<br>FspsUpd structure do not exist in the github version, but they are kept<br>here because they are used by coreboot and are not causing problems when<br>set as it only changed UnusedUpdSpace in the github UPD.<br><br>The MEMORY_INFO_DATA_HOB structure has its EfiHobGuidType field removed<br>because hob_header_to_extension_hob in drivers/intel/fsp2_0/<br>called by fsp_find_extension_hob_by_guid will actually remove it before<br>returning the structure pointer.<br><br>[1] https://github.com/IntelFsp/FSP/tree/Kabylake/KabylakeFspBinPkg<br><br>Change-Id: I233bf7cf6f62e9e1b389d42a09461717a3285f0f<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h<br>1 file changed, 1 insertion(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/26108/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h</span><br><span>index 248b4d5..629cee4 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h</span><br><span>@@ -170,13 +170,6 @@</span><br><span> UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.</span><br><span> } MRC_CH_TIMING;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-typedef struct {</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.</span><br><span style="color: hsl(0, 100%, 40%);">-} MRC_TA_TIMING;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> ///</span><br><span> /// Memory SMBIOS & OC Memory Data Hob</span><br><span> ///</span><br><span>@@ -207,10 +200,6 @@</span><br><span> UINT8 RevisionId; ///< The PCI revision id of this memory controller.</span><br><span> UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.</span><br><span> CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings</span><br><span style="color: hsl(0, 100%, 40%);">- MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings</span><br><span> } CONTROLLER_INFO;</span><br><span> </span><br><span> typedef struct {</span><br><span>@@ -228,6 +217,7 @@</span><br><span> UINT8 ErrorCorrectionType;</span><br><span> </span><br><span> SiMrcVersion Version;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 FreqMax;</span><br><span> BOOLEAN EccSupport;</span><br><span> UINT8 MemoryProfile;</span><br><span> UINT32 TotalPhysicalMemorySize;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26108">change 26108</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26108"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I233bf7cf6f62e9e1b389d42a09461717a3285f0f </div>
<div style="display:none"> Gerrit-Change-Number: 26108 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> </div>