[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Use common gspi code and remove it from soc

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26049


Change subject: soc/intel/cannonlake: Use common gspi code and remove it from soc
......................................................................

soc/intel/cannonlake: Use common gspi code and remove it from soc

Use common gspi code which was added for cannonlake PCH and remove it
from cannonlake soc. Soc needs to implement one function which returns
soc specific gspi configuration which has been implemented inside
chip_config.c file.

Also enabling selection of block gspi using common code which was not
enabled in previous patch.

BUG=none
BRANCH=none
TEST=code compiles with different configurations.

Change-Id: I76ea50072a40563ea1de048546bd847ceac7fd28
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip_config.c
M src/soc/intel/common/basecode/pch/Kconfig
4 files changed, 19 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/26049/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index e21a8fe..6c76d34 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -55,7 +55,6 @@
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GPIO
 	select SOC_INTEL_COMMON_BLOCK_GRAPHICS
-	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_ITSS
 	select SOC_INTEL_COMMON_BLOCK_LPC
 	select SOC_INTEL_COMMON_BLOCK_LPSS
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 713ffc1..e6dc3ca 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -14,7 +14,6 @@
 bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += gpio.c
-bootblock-y += gspi.c
 bootblock-y += chip_config.c
 bootblock-y += memmap.c
 bootblock-y += spi.c
@@ -24,7 +23,6 @@
 romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
 romstage-y += chip_config.c
 romstage-y += gpio.c
-romstage-y += gspi.c
 romstage-y += lpc.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
@@ -38,7 +36,6 @@
 ramstage-y += finalize.c
 ramstage-y += gpio.c
 ramstage-y += graphics.c
-ramstage-y += gspi.c
 ramstage-y += gpio.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
@@ -63,7 +60,6 @@
 postcar-y += pmutil.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c
 
-verstage-y += gspi.c
 verstage-y += chip_config.c
 verstage-y += pmutil.c
 verstage-y += spi.c
diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c
index 2ccd945..985948d 100644
--- a/src/soc/intel/cannonlake/chip_config.c
+++ b/src/soc/intel/cannonlake/chip_config.c
@@ -17,6 +17,7 @@
 #include <device/device.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelbasecode/lockdown.h>
+#include <intelblocks/gspi.h>
 
 /*
  * This function will return SOC specific lockdown configuration.
@@ -53,3 +54,20 @@
 
 	return &config->i2c[bus];
 }
+
+const struct gspi_cfg *gspi_get_soc_cfg(void)
+{
+	DEVTREE_CONST struct soc_intel_cannonlake_config *config;
+	int devfn = SA_DEVFN_ROOT;
+	DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
+
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+		       __func__);
+		return NULL;
+	}
+
+	config = dev->chip_info;
+
+	return &config->gspi[0];
+}
diff --git a/src/soc/intel/common/basecode/pch/Kconfig b/src/soc/intel/common/basecode/pch/Kconfig
index 19870db..31e2136 100644
--- a/src/soc/intel/common/basecode/pch/Kconfig
+++ b/src/soc/intel/common/basecode/pch/Kconfig
@@ -2,6 +2,7 @@
 	bool
 	default n
 	select SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C
+	select SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI
 	help
 	  "Select Cannonlake point PCH base support. SOC may select this config
 	   to avail common PCH code"

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I76ea50072a40563ea1de048546bd847ceac7fd28
Gerrit-Change-Number: 26049
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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