<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26049">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Use common gspi code and remove it from soc<br><br>Use common gspi code which was added for cannonlake PCH and remove it<br>from cannonlake soc. Soc needs to implement one function which returns<br>soc specific gspi configuration which has been implemented inside<br>chip_config.c file.<br><br>Also enabling selection of block gspi using common code which was not<br>enabled in previous patch.<br><br>BUG=none<br>BRANCH=none<br>TEST=code compiles with different configurations.<br><br>Change-Id: I76ea50072a40563ea1de048546bd847ceac7fd28<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip_config.c<br>M src/soc/intel/common/basecode/pch/Kconfig<br>4 files changed, 19 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/26049/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index e21a8fe..6c76d34 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -55,7 +55,6 @@</span><br><span> select SOC_INTEL_COMMON_BLOCK_FAST_SPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_GPIO</span><br><span> select SOC_INTEL_COMMON_BLOCK_GRAPHICS</span><br><span style="color: hsl(0, 100%, 40%);">- select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2</span><br><span> select SOC_INTEL_COMMON_BLOCK_ITSS</span><br><span> select SOC_INTEL_COMMON_BLOCK_LPC</span><br><span> select SOC_INTEL_COMMON_BLOCK_LPSS</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 713ffc1..e6dc3ca 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -14,7 +14,6 @@</span><br><span> bootblock-y += pmutil.c</span><br><span> bootblock-y += bootblock/report_platform.c</span><br><span> bootblock-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += gspi.c</span><br><span> bootblock-y += chip_config.c</span><br><span> bootblock-y += memmap.c</span><br><span> bootblock-y += spi.c</span><br><span>@@ -24,7 +23,6 @@</span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c</span><br><span> romstage-y += chip_config.c</span><br><span> romstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += gspi.c</span><br><span> romstage-y += lpc.c</span><br><span> romstage-y += memmap.c</span><br><span> romstage-y += pmutil.c</span><br><span>@@ -38,7 +36,6 @@</span><br><span> ramstage-y += finalize.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += graphics.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += gspi.c</span><br><span> ramstage-y += gpio.c</span><br><span> ramstage-y += lpc.c</span><br><span> ramstage-y += memmap.c</span><br><span>@@ -63,7 +60,6 @@</span><br><span> postcar-y += pmutil.c</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-verstage-y += gspi.c</span><br><span> verstage-y += chip_config.c</span><br><span> verstage-y += pmutil.c</span><br><span> verstage-y += spi.c</span><br><span>diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c</span><br><span>index 2ccd945..985948d 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip_config.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip_config.c</span><br><span>@@ -17,6 +17,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <drivers/i2c/designware/dw_i2c.h></span><br><span> #include <intelbasecode/lockdown.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span> </span><br><span> /*</span><br><span> * This function will return SOC specific lockdown configuration.</span><br><span>@@ -53,3 +54,20 @@</span><br><span> </span><br><span> return &config->i2c[bus];</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct gspi_cfg *gspi_get_soc_cfg(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ int devfn = SA_DEVFN_ROOT;</span><br><span style="color: hsl(120, 100%, 40%);">+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return &config->gspi[0];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/common/basecode/pch/Kconfig b/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>index 19870db..31e2136 100644</span><br><span>--- a/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>+++ b/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>@@ -2,6 +2,7 @@</span><br><span> bool</span><br><span> default n</span><br><span> select SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI</span><br><span> help</span><br><span> "Select Cannonlake point PCH base support. SOC may select this config</span><br><span> to avail common PCH code"</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26049">change 26049</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26049"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I76ea50072a40563ea1de048546bd847ceac7fd28 </div>
<div style="display:none"> Gerrit-Change-Number: 26049 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>