[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/basecode: Add support for common GSPI for CNL PCH

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26048


Change subject: soc/intel/common/basecode: Add support for common GSPI for CNL PCH
......................................................................

soc/intel/common/basecode: Add support for common GSPI for CNL PCH

Add support for common GSPI code for cannonlake pch configuration. This
will allow us to use common gspi code across multiple soc which uses
same pch configuration.

when soc selects, "SOC_INTEL_COMMON_BASECODE_PCH_CNP" this code will
also get selected automatically.

BUG=none
BRANCH=none
TEST=code compiles with different configurations

Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/common/basecode/pch/Kconfig
M src/soc/intel/common/basecode/pch/Makefile.inc
A src/soc/intel/common/basecode/pch/gspi.c
3 files changed, 72 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26048/1

diff --git a/src/soc/intel/common/basecode/pch/Kconfig b/src/soc/intel/common/basecode/pch/Kconfig
index 7357d55..19870db 100644
--- a/src/soc/intel/common/basecode/pch/Kconfig
+++ b/src/soc/intel/common/basecode/pch/Kconfig
@@ -13,3 +13,11 @@
 	help
 	  "Select common Cannonlake PCH i2c support. SOC will use this code when
 	   it avails common pch code"
+
+config SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI
+	bool
+	default n
+	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
+	help
+	  "Select common Cannonlake PCH gspi support. SOC will use this code when
+	   it avails common pch code"
diff --git a/src/soc/intel/common/basecode/pch/Makefile.inc b/src/soc/intel/common/basecode/pch/Makefile.inc
index 72701d7..6b98225 100644
--- a/src/soc/intel/common/basecode/pch/Makefile.inc
+++ b/src/soc/intel/common/basecode/pch/Makefile.inc
@@ -1,4 +1,11 @@
-bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
-verstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c
+
+romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c
+
+verstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c
diff --git a/src/soc/intel/common/basecode/pch/gspi.c b/src/soc/intel/common/basecode/pch/gspi.c
new file mode 100644
index 0000000..747c9ce
--- /dev/null
+++ b/src/soc/intel/common/basecode/pch/gspi.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/spi.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+
+uintptr_t gspi_get_soc_early_base(void)
+{
+	return EARLY_GSPI_BASE_ADDRESS;
+}
+
+/*
+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
+ * the bus # accordingly when referring to SPI / GSPI bus numbers.
+ */
+#define GSPI_TO_SPI_BUS(x)	((x) + 1)
+#define SPI_TO_GSPI_BUS(x)	((x) - 1)
+
+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
+{
+	if (spi_bus == 0)
+		return -1;
+
+	*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
+	if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+		return -1;
+
+	return 0;
+}
+
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
+{
+	if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
+		return -1;
+
+	return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb
Gerrit-Change-Number: 26048
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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