<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26048">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/basecode: Add support for common GSPI for CNL PCH<br><br>Add support for common GSPI code for cannonlake pch configuration. This<br>will allow us to use common gspi code across multiple soc which uses<br>same pch configuration.<br><br>when soc selects, "SOC_INTEL_COMMON_BASECODE_PCH_CNP" this code will<br>also get selected automatically.<br><br>BUG=none<br>BRANCH=none<br>TEST=code compiles with different configurations<br><br>Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/common/basecode/pch/Kconfig<br>M src/soc/intel/common/basecode/pch/Makefile.inc<br>A src/soc/intel/common/basecode/pch/gspi.c<br>3 files changed, 72 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/26048/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/basecode/pch/Kconfig b/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>index 7357d55..19870db 100644</span><br><span>--- a/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>+++ b/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>@@ -13,3 +13,11 @@</span><br><span> help</span><br><span> "Select common Cannonlake PCH i2c support. SOC will use this code when</span><br><span> it avails common pch code"</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ "Select common Cannonlake PCH gspi support. SOC will use this code when</span><br><span style="color: hsl(120, 100%, 40%);">+ it avails common pch code"</span><br><span>diff --git a/src/soc/intel/common/basecode/pch/Makefile.inc b/src/soc/intel/common/basecode/pch/Makefile.inc</span><br><span>index 72701d7..6b98225 100644</span><br><span>--- a/src/soc/intel/common/basecode/pch/Makefile.inc</span><br><span>+++ b/src/soc/intel/common/basecode/pch/Makefile.inc</span><br><span>@@ -1,4 +1,11 @@</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c</span><br><span style="color: hsl(0, 100%, 40%);">-verstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C) += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_GSPI) += gspi.c</span><br><span>diff --git a/src/soc/intel/common/basecode/pch/gspi.c b/src/soc/intel/common/basecode/pch/gspi.c</span><br><span>new file mode 100644</span><br><span>index 0000000..747c9ce</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/pch/gspi.c</span><br><span>@@ -0,0 +1,53 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2017 Google Inc.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; either version 2 of the License, or</span><br><span style="color: hsl(120, 100%, 40%);">+ * (at your option) any later version.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <assert.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/gspi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/iomap.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pci_devs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+uintptr_t gspi_get_soc_early_base(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ return EARLY_GSPI_BASE_ADDRESS;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust</span><br><span style="color: hsl(120, 100%, 40%);">+ * the bus # accordingly when referring to SPI / GSPI bus numbers.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#define GSPI_TO_SPI_BUS(x) ((x) + 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_TO_GSPI_BUS(x) ((x) - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (spi_bus == 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return spi_soc_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26048">change 26048</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26048"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb </div>
<div style="display:none"> Gerrit-Change-Number: 26048 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>