[coreboot-gerrit] Change in coreboot[master]: src/southbridge: Add space befor open '('

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26035


Change subject: src/southbridge: Add space befor open '('
......................................................................

src/southbridge: Add space befor open '('

Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/southbridge/amd/sr5650/early_setup.c
M src/southbridge/broadcom/bcm5785/lpc.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/fsp_bd82x6x/me_8.x.c
M src/southbridge/intel/fsp_i89xx/me_8.x.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/nvidia/mcp55/lpc.c
M src/southbridge/sis/sis966/lpc.c
M src/southbridge/sis/sis966/sis966.c
9 files changed, 9 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26035/1

diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 98b60fd..57a300c 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -104,7 +104,7 @@
 {
 	u8 reg;
 	reg = pci_read_config8(nb_dev, 0x8);	/* copy from CIM, can't find in doc */
-	switch(reg & 3)
+	switch (reg & 3)
 	{
 	case 0x00:
 		reg = REV_SR5650_A11;
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index cc285a3..05dbbc3 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -84,7 +84,7 @@
 					base = res->base;
 					end = resource_end(res);
 					printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
-					switch(base) {
+					switch (base) {
 					case 0x60: //KBC
 					case 0x64:
 						reg |= (1<<29); break;
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 6463f96..54a16ce 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -864,7 +864,7 @@
 		p = &mbp_item_hdr;
 		printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
 
-		switch(mbp_item_id) {
+		switch (mbp_item_id) {
 		case 0x101:
 			SET_UP_COPY(fw_version_name);
 
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index d89502e..fd8b167 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -861,7 +861,7 @@
 		p = &mbp_item_hdr;
 		printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
 
-		switch(mbp_item_id) {
+		switch (mbp_item_id) {
 		case 0x101:
 			SET_UP_COPY(fw_version_name);
 
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index b094524..b77cad2 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -816,7 +816,7 @@
 		p = &mbp_item_hdr;
 		printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));
 
-		switch(mbp_item_id) {
+		switch (mbp_item_id) {
 		case 0x101:
 			SET_UP_COPY(fw_version_name);
 
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index c393feb..6168498 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -1016,7 +1016,7 @@
 	for (i = 0; i < mbp->header.mbp_size - 1;) {
 		mbp_item_header *item = (void *)&mbp->data[i];
 
-		switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) {
+		switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
 		case MBP_IDENT(KERNEL, FW_VER):
 			ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);
 
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 180b9a8..ba9386b 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -197,7 +197,7 @@
 					base = res->base;
 					end = resource_end(res);
 					printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
-					switch(base) {
+					switch (base) {
 					case 0x3f8: /* COM1 */
 						reg |= (1 << 0);
 						break;
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 40dc705..82b850b 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -203,7 +203,7 @@
 					base = res->base;
 					end = resource_end(res);
 					printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
-					switch(base) {
+					switch (base) {
 					case 0x3f8: // COM1
 						reg |= (1<<0);	break;
 					case 0x2f8: // COM2
diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c
index d84b373..cba4898 100644
--- a/src/southbridge/sis/sis966/sis966.c
+++ b/src/southbridge/sis/sis966/sis966.c
@@ -80,7 +80,7 @@
 	}
 
 	devfn = (dev->path.pci.devfn) & ~7;
-	switch(deviceid) {
+	switch (deviceid) {
 		case PCI_DEVICE_ID_SIS_SIS966_USB:
 			devfn -= (1<<3);
 			index = 8;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7
Gerrit-Change-Number: 26035
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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