<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26035">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/southbridge: Add space befor open '('<br><br>Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/southbridge/amd/sr5650/early_setup.c<br>M src/southbridge/broadcom/bcm5785/lpc.c<br>M src/southbridge/intel/bd82x6x/me_8.x.c<br>M src/southbridge/intel/fsp_bd82x6x/me_8.x.c<br>M src/southbridge/intel/fsp_i89xx/me_8.x.c<br>M src/southbridge/intel/lynxpoint/me_9.x.c<br>M src/southbridge/nvidia/mcp55/lpc.c<br>M src/southbridge/sis/sis966/lpc.c<br>M src/southbridge/sis/sis966/sis966.c<br>9 files changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/26035/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c</span><br><span>index 98b60fd..57a300c 100644</span><br><span>--- a/src/southbridge/amd/sr5650/early_setup.c</span><br><span>+++ b/src/southbridge/amd/sr5650/early_setup.c</span><br><span>@@ -104,7 +104,7 @@</span><br><span> {</span><br><span> u8 reg;</span><br><span> reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */</span><br><span style="color: hsl(0, 100%, 40%);">- switch(reg & 3)</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (reg & 3)</span><br><span> {</span><br><span> case 0x00:</span><br><span> reg = REV_SR5650_A11;</span><br><span>diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c</span><br><span>index cc285a3..05dbbc3 100644</span><br><span>--- a/src/southbridge/broadcom/bcm5785/lpc.c</span><br><span>+++ b/src/southbridge/broadcom/bcm5785/lpc.c</span><br><span>@@ -84,7 +84,7 @@</span><br><span> base = res->base;</span><br><span> end = resource_end(res);</span><br><span> printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);</span><br><span style="color: hsl(0, 100%, 40%);">- switch(base) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (base) {</span><br><span> case 0x60: //KBC</span><br><span> case 0x64:</span><br><span> reg |= (1<<29); break;</span><br><span>diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>index 6463f96..54a16ce 100644</span><br><span>--- a/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>+++ b/src/southbridge/intel/bd82x6x/me_8.x.c</span><br><span>@@ -864,7 +864,7 @@</span><br><span> p = &mbp_item_hdr;</span><br><span> printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- switch(mbp_item_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (mbp_item_id) {</span><br><span> case 0x101:</span><br><span> SET_UP_COPY(fw_version_name);</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c</span><br><span>index d89502e..fd8b167 100644</span><br><span>--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c</span><br><span>+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c</span><br><span>@@ -861,7 +861,7 @@</span><br><span> p = &mbp_item_hdr;</span><br><span> printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- switch(mbp_item_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (mbp_item_id) {</span><br><span> case 0x101:</span><br><span> SET_UP_COPY(fw_version_name);</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c</span><br><span>index b094524..b77cad2 100644</span><br><span>--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c</span><br><span>+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c</span><br><span>@@ -816,7 +816,7 @@</span><br><span> p = &mbp_item_hdr;</span><br><span> printk(BIOS_INFO, "ME: MBP item header %8.8x\n", *((u32*)p));</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- switch(mbp_item_id) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (mbp_item_id) {</span><br><span> case 0x101:</span><br><span> SET_UP_COPY(fw_version_name);</span><br><span> </span><br><span>diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>index c393feb..6168498 100644</span><br><span>--- a/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>+++ b/src/southbridge/intel/lynxpoint/me_9.x.c</span><br><span>@@ -1016,7 +1016,7 @@</span><br><span> for (i = 0; i < mbp->header.mbp_size - 1;) {</span><br><span> mbp_item_header *item = (void *)&mbp->data[i];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {</span><br><span> case MBP_IDENT(KERNEL, FW_VER):</span><br><span> ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);</span><br><span> </span><br><span>diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c</span><br><span>index 180b9a8..ba9386b 100644</span><br><span>--- a/src/southbridge/nvidia/mcp55/lpc.c</span><br><span>+++ b/src/southbridge/nvidia/mcp55/lpc.c</span><br><span>@@ -197,7 +197,7 @@</span><br><span> base = res->base;</span><br><span> end = resource_end(res);</span><br><span> printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);</span><br><span style="color: hsl(0, 100%, 40%);">- switch(base) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (base) {</span><br><span> case 0x3f8: /* COM1 */</span><br><span> reg |= (1 << 0);</span><br><span> break;</span><br><span>diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c</span><br><span>index 40dc705..82b850b 100644</span><br><span>--- a/src/southbridge/sis/sis966/lpc.c</span><br><span>+++ b/src/southbridge/sis/sis966/lpc.c</span><br><span>@@ -203,7 +203,7 @@</span><br><span> base = res->base;</span><br><span> end = resource_end(res);</span><br><span> printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);</span><br><span style="color: hsl(0, 100%, 40%);">- switch(base) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (base) {</span><br><span> case 0x3f8: // COM1</span><br><span> reg |= (1<<0); break;</span><br><span> case 0x2f8: // COM2</span><br><span>diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c</span><br><span>index d84b373..cba4898 100644</span><br><span>--- a/src/southbridge/sis/sis966/sis966.c</span><br><span>+++ b/src/southbridge/sis/sis966/sis966.c</span><br><span>@@ -80,7 +80,7 @@</span><br><span> }</span><br><span> </span><br><span> devfn = (dev->path.pci.devfn) & ~7;</span><br><span style="color: hsl(0, 100%, 40%);">- switch(deviceid) {</span><br><span style="color: hsl(120, 100%, 40%);">+ switch (deviceid) {</span><br><span> case PCI_DEVICE_ID_SIS_SIS966_USB:</span><br><span> devfn -= (1<<3);</span><br><span> index = 8;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26035">change 26035</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7 </div>
<div style="display:none"> Gerrit-Change-Number: 26035 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>