[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Use common i2c support for CNL PCH
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Thu May 3 12:04:02 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26030
Change subject: soc/intel/cannonlake: Use common i2c support for CNL PCH
......................................................................
soc/intel/cannonlake: Use common i2c support for CNL PCH
In previous patch, common i2c support was added for soc which uses same
configurations as cannonlake pch. For cannonlake soc, we'll switch to common
i2c support and remove code from soc folder. This will allow us to
reduce redundant copy of common code across multiple soc.
When common i2c support is used, soc needs to implement one function for
i2c which returns soc specific configuration for the IP. This function
is implemented inside chip_config.c file which will have all the chip
specific information.
BUG=none
BRANCH=none
TEST=code compiles with different configurations. No changes in code
logic.
Change-Id: I95b3d1b2b0dfd5fb49859ddf5c42fee44b16dd8c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip_config.c
D src/soc/intel/cannonlake/i2c.c
4 files changed, 23 insertions(+), 87 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/26030/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index ebf6741..8bdcf99 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -44,6 +44,7 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BASECODE_LOCKDOWN
+ select SOC_INTEL_COMMON_BASECODE_PCH_CNP
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 0e73c14..713ffc1 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -15,16 +15,16 @@
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
bootblock-y += gspi.c
-bootblock-y += i2c.c
+bootblock-y += chip_config.c
bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
+romstage-y += chip_config.c
romstage-y += gpio.c
romstage-y += gspi.c
-romstage-y += i2c.c
romstage-y += lpc.c
romstage-y += memmap.c
romstage-y += pmutil.c
@@ -40,7 +40,6 @@
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += gpio.c
-ramstage-y += i2c.c
ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += nhlt.c
@@ -65,7 +64,7 @@
postcar-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c
-verstage-y += i2c.c
+verstage-y += chip_config.c
verstage-y += pmutil.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c
index 679c062..2ccd945 100644
--- a/src/soc/intel/cannonlake/chip_config.c
+++ b/src/soc/intel/cannonlake/chip_config.c
@@ -13,7 +13,9 @@
* GNU General Public License for more details.
*/
#include "chip.h"
+#include <console/console.h>
#include <device/device.h>
+#include <drivers/i2c/designware/dw_i2c.h>
#include <intelbasecode/lockdown.h>
/*
@@ -26,7 +28,7 @@
int soc_get_lockdown_config(void)
{
const struct soc_intel_cannonlake_config *config;
- struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
if (dev == NULL || dev->chip_info == NULL)
return -1;
@@ -35,3 +37,19 @@
return config->chipset_lockdown;
}
+
+const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
+{
+ const struct soc_intel_cannonlake_config *config;
+ const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+ __func__);
+ return NULL;
+ }
+
+ config = dev->chip_info;
+
+ return &config->i2c[bus];
+}
diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c
deleted file mode 100644
index ef30345..0000000
--- a/src/soc/intel/cannonlake/i2c.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include "chip.h"
-
-const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
-{
- const struct soc_intel_cannonlake_config *config;
- const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
-
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
- __func__);
- return NULL;
- }
-
- config = dev->chip_info;
-
- return &config->i2c[bus];
-}
-
-uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)
-{
- return EARLY_I2C_BASE(bus);
-}
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
- switch (devfn) {
- case PCH_DEVFN_I2C0:
- return 0;
- case PCH_DEVFN_I2C1:
- return 1;
- case PCH_DEVFN_I2C2:
- return 2;
- case PCH_DEVFN_I2C3:
- return 3;
- case PCH_DEVFN_I2C4:
- return 4;
- case PCH_DEVFN_I2C5:
- return 5;
- }
- return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
- switch (bus) {
- case 0:
- return PCH_DEVFN_I2C0;
- case 1:
- return PCH_DEVFN_I2C1;
- case 2:
- return PCH_DEVFN_I2C2;
- case 3:
- return PCH_DEVFN_I2C3;
- case 4:
- return PCH_DEVFN_I2C4;
- case 5:
- return PCH_DEVFN_I2C5;
- }
- return -1;
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I95b3d1b2b0dfd5fb49859ddf5c42fee44b16dd8c
Gerrit-Change-Number: 26030
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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