<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26030">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Use common i2c support for CNL PCH<br><br>In previous patch, common i2c support was added for soc which uses same<br>configurations as cannonlake pch. For cannonlake soc, we'll switch to common<br>i2c support and remove code from soc folder. This will allow us to<br>reduce redundant copy of common code across multiple soc.<br><br>When common i2c support is used, soc needs to implement one function for<br>i2c which returns soc specific configuration for the IP. This function<br>is implemented inside chip_config.c file which will have all the chip<br>specific information.<br><br>BUG=none<br>BRANCH=none<br>TEST=code compiles with different configurations. No changes in code<br>logic.<br><br>Change-Id: I95b3d1b2b0dfd5fb49859ddf5c42fee44b16dd8c<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip_config.c<br>D src/soc/intel/cannonlake/i2c.c<br>4 files changed, 23 insertions(+), 87 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/26030/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index ebf6741..8bdcf99 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -44,6 +44,7 @@</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span> select SOC_INTEL_COMMON_BASECODE</span><br><span> select SOC_INTEL_COMMON_BASECODE_LOCKDOWN</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_PCH_CNP</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_ACPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 0e73c14..713ffc1 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -15,16 +15,16 @@</span><br><span> bootblock-y += bootblock/report_platform.c</span><br><span> bootblock-y += gpio.c</span><br><span> bootblock-y += gspi.c</span><br><span style="color: hsl(0, 100%, 40%);">-bootblock-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+bootblock-y += chip_config.c</span><br><span> bootblock-y += memmap.c</span><br><span> bootblock-y += spi.c</span><br><span> bootblock-y += lpc.c</span><br><span> bootblock-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c</span><br><span style="color: hsl(120, 100%, 40%);">+romstage-y += chip_config.c</span><br><span> romstage-y += gpio.c</span><br><span> romstage-y += gspi.c</span><br><span style="color: hsl(0, 100%, 40%);">-romstage-y += i2c.c</span><br><span> romstage-y += lpc.c</span><br><span> romstage-y += memmap.c</span><br><span> romstage-y += pmutil.c</span><br><span>@@ -40,7 +40,6 @@</span><br><span> ramstage-y += graphics.c</span><br><span> ramstage-y += gspi.c</span><br><span> ramstage-y += gpio.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += i2c.c</span><br><span> ramstage-y += lpc.c</span><br><span> ramstage-y += memmap.c</span><br><span> ramstage-y += nhlt.c</span><br><span>@@ -65,7 +64,7 @@</span><br><span> postcar-$(CONFIG_UART_DEBUG) += uart.c</span><br><span> </span><br><span> verstage-y += gspi.c</span><br><span style="color: hsl(0, 100%, 40%);">-verstage-y += i2c.c</span><br><span style="color: hsl(120, 100%, 40%);">+verstage-y += chip_config.c</span><br><span> verstage-y += pmutil.c</span><br><span> verstage-y += spi.c</span><br><span> verstage-$(CONFIG_UART_DEBUG) += uart.c</span><br><span>diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c</span><br><span>index 679c062..2ccd945 100644</span><br><span>--- a/src/soc/intel/cannonlake/chip_config.c</span><br><span>+++ b/src/soc/intel/cannonlake/chip_config.c</span><br><span>@@ -13,7 +13,9 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> #include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span> #include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <drivers/i2c/designware/dw_i2c.h></span><br><span> #include <intelbasecode/lockdown.h></span><br><span> </span><br><span> /*</span><br><span>@@ -26,7 +28,7 @@</span><br><span> int soc_get_lockdown_config(void)</span><br><span> {</span><br><span> const struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span> </span><br><span> if (dev == NULL || dev->chip_info == NULL)</span><br><span> return -1;</span><br><span>@@ -35,3 +37,19 @@</span><br><span> </span><br><span> return config->chipset_lockdown;</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+ return NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return &config->i2c[bus];</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c</span><br><span>deleted file mode 100644</span><br><span>index ef30345..0000000</span><br><span>--- a/src/soc/intel/cannonlake/i2c.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,82 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright 2016 Google Inc.</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <console/console.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/device.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <device/pci_def.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <drivers/i2c/designware/dw_i2c.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/iomap.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include "chip.h"</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- const struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(0, 100%, 40%);">- const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (!dev || !dev->chip_info) {</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",</span><br><span style="color: hsl(0, 100%, 40%);">- __func__);</span><br><span style="color: hsl(0, 100%, 40%);">- return NULL;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- return &config->i2c[bus];</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- return EARLY_I2C_BASE(bus);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- switch (devfn) {</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C0:</span><br><span style="color: hsl(0, 100%, 40%);">- return 0;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C1:</span><br><span style="color: hsl(0, 100%, 40%);">- return 1;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C2:</span><br><span style="color: hsl(0, 100%, 40%);">- return 2;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C3:</span><br><span style="color: hsl(0, 100%, 40%);">- return 3;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C4:</span><br><span style="color: hsl(0, 100%, 40%);">- return 4;</span><br><span style="color: hsl(0, 100%, 40%);">- case PCH_DEVFN_I2C5:</span><br><span style="color: hsl(0, 100%, 40%);">- return 5;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-int dw_i2c_soc_bus_to_devfn(unsigned int bus)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- switch (bus) {</span><br><span style="color: hsl(0, 100%, 40%);">- case 0:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C0;</span><br><span style="color: hsl(0, 100%, 40%);">- case 1:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C1;</span><br><span style="color: hsl(0, 100%, 40%);">- case 2:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C2;</span><br><span style="color: hsl(0, 100%, 40%);">- case 3:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C3;</span><br><span style="color: hsl(0, 100%, 40%);">- case 4:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C4;</span><br><span style="color: hsl(0, 100%, 40%);">- case 5:</span><br><span style="color: hsl(0, 100%, 40%);">- return PCH_DEVFN_I2C5;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">- return -1;</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26030">change 26030</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26030"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I95b3d1b2b0dfd5fb49859ddf5c42fee44b16dd8c </div>
<div style="display:none"> Gerrit-Change-Number: 26030 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>