[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/basecode: Add common I2C support for CNL PCH

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26029


Change subject: soc/intel/common/basecode: Add common I2C support for CNL PCH
......................................................................

soc/intel/common/basecode: Add common I2C support for CNL PCH

I2C configuration depends on PCH, so if more than one SOC uses same PCH
configuration, code for I2C will be common across those SOC.

Since we keep i2c code in soc, it increases amount of code copy during
creation of new soc. Thus making code common will allow us to use common
i2c functionality across multiple SOCs. Once User selects
"CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP", it'll use i2c function from
common pool and soc will only need to implement function which returns
soc specific i2c configuration.

BUG=none
BRANCH=none
TEST= code compiles with different configurations

Change-Id: Ie77b213026e6a76ba50de2ba16240a72ee3e6416
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/common/basecode/pch/Kconfig
A src/soc/intel/common/basecode/pch/Makefile.inc
A src/soc/intel/common/basecode/pch/i2c.c
3 files changed, 77 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/26029/1

diff --git a/src/soc/intel/common/basecode/pch/Kconfig b/src/soc/intel/common/basecode/pch/Kconfig
index 7372a56..e755d31 100644
--- a/src/soc/intel/common/basecode/pch/Kconfig
+++ b/src/soc/intel/common/basecode/pch/Kconfig
@@ -1,5 +1,14 @@
 config SOC_INTEL_COMMON_BASECODE_PCH_CNP
 	bool
 	default n
+	select SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C
 	help
-	  "Select CNL PCH support for the SOC"
+	  "Select support for CNL PCH common code"
+
+config SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C
+	bool
+	default n
+	select SOC_INTEL_COMMON_BLOCK_I2C
+	help
+	  "Selects support for CNL PCH I2C block. This block is common across
+	   SOC which uses CNL PCH"
diff --git a/src/soc/intel/common/basecode/pch/Makefile.inc b/src/soc/intel/common/basecode/pch/Makefile.inc
new file mode 100644
index 0000000..72701d7
--- /dev/null
+++ b/src/soc/intel/common/basecode/pch/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
+verstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_I2C)+=i2c.c
diff --git a/src/soc/intel/common/basecode/pch/i2c.c b/src/soc/intel/common/basecode/pch/i2c.c
new file mode 100644
index 0000000..e6bcd9a
--- /dev/null
+++ b/src/soc/intel/common/basecode/pch/i2c.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <drivers/i2c/designware/dw_i2c.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+
+uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)
+{
+	return EARLY_I2C_BASE(bus);
+}
+
+int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
+{
+	switch (devfn) {
+	case PCH_DEVFN_I2C0:
+		return 0;
+	case PCH_DEVFN_I2C1:
+		return 1;
+	case PCH_DEVFN_I2C2:
+		return 2;
+	case PCH_DEVFN_I2C3:
+		return 3;
+	case PCH_DEVFN_I2C4:
+		return 4;
+	case PCH_DEVFN_I2C5:
+		return 5;
+	}
+	return -1;
+}
+
+int dw_i2c_soc_bus_to_devfn(unsigned int bus)
+{
+	switch (bus) {
+	case 0:
+		return PCH_DEVFN_I2C0;
+	case 1:
+		return PCH_DEVFN_I2C1;
+	case 2:
+		return PCH_DEVFN_I2C2;
+	case 3:
+		return PCH_DEVFN_I2C3;
+	case 4:
+		return PCH_DEVFN_I2C4;
+	case 5:
+		return PCH_DEVFN_I2C5;
+	}
+	return -1;
+}

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie77b213026e6a76ba50de2ba16240a72ee3e6416
Gerrit-Change-Number: 26029
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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