[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/basecode: Add new folder PCH for common code
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Thu May 3 11:30:23 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26026
Change subject: soc/intel/common/basecode: Add new folder PCH for common code
......................................................................
soc/intel/common/basecode: Add new folder PCH for common code
Create a new folder named "pch" inside basecode directory which will
contain common code which relies on PCH. Currently adding support for
CNL PCH known as CNP.
In this patch, creating common lockdown file inside PCH. When user
selects "SOC_INTEL_COMMON_BASECODE_PCH_CNP" kconfig then it
automatically selects lockdown file from basecode instead of using it
from PCH. This also requires soc to implement soc specific function
which returns soc specific lockdown configuration.
BUG=none
BRANCH=none
TEST=code compiles with different configurations
Change-Id: I3587d8fd69c6ac7d3d772401969258c3f3600809
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
A src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h
A src/soc/intel/common/basecode/pch/Kconfig
A src/soc/intel/common/basecode/pch/Makefile.inc
A src/soc/intel/common/basecode/pch/lockdown.c
4 files changed, 151 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/26026/1
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h b/src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h
new file mode 100644
index 0000000..d16e23c
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BASECODE_PCH_LOCKDOWN_H
+#define SOC_INTEL_COMMON_BASECODE_PCH_LOCKDOWN_H
+
+/*
+ * This function will get lockdown config specific to soc.
+ * Each SOC using lockdown functionality should implement following strong
+ * function which returns proper lockdown config value.
+ *
+ * Return values:
+ * -1 = Error = Unable to find device
+ * 0 = CHIPSET_LOCKDOWN_FSP = use FSP's lockdown functionality to lockdown Ips
+ * 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown IPs
+ */
+int soc_get_lockdown_config(void);
+
+#endif
diff --git a/src/soc/intel/common/basecode/pch/Kconfig b/src/soc/intel/common/basecode/pch/Kconfig
new file mode 100644
index 0000000..b7a176b
--- /dev/null
+++ b/src/soc/intel/common/basecode/pch/Kconfig
@@ -0,0 +1,10 @@
+config SOC_INTEL_COMMON_BASECODE_PCH_CNP
+ bool
+ default n
+ select SOC_INTEL_COMMON_BASECODE_PCH_CNP_LOCKDOWN
+
+config SOC_INTEL_COMMON_BASECODE_PCH_CNP_LOCKDOWN
+ bool
+ default n
+ help
+ "Use lockdown from common block basecode instead of soc"
diff --git a/src/soc/intel/common/basecode/pch/Makefile.inc b/src/soc/intel/common/basecode/pch/Makefile.inc
new file mode 100644
index 0000000..e99c5b9
--- /dev/null
+++ b/src/soc/intel/common/basecode/pch/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_LOCKDOWN)+= lockdown.c
diff --git a/src/soc/intel/common/basecode/pch/lockdown.c b/src/soc/intel/common/basecode/pch/lockdown.c
new file mode 100644
index 0000000..d60fbee
--- /dev/null
+++ b/src/soc/intel/common/basecode/pch/lockdown.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <bootstate.h>
+#include "chip.h"
+#include <intelbasecode/pch/lockdown.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <string.h>
+
+#define PCR_DMI_GCS 0x274C
+#define PCR_DMI_GCS_BILD (1 << 0)
+
+static void pmc_lockdown_cfg(int chipset_lockdown)
+{
+ uint8_t *pmcbase, reg8;
+ uint32_t reg32, pmsyncreg;
+
+ /* PMSYNC */
+ pmcbase = pmc_mmio_regs();
+ pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
+ pmsyncreg |= PMSYNC_LOCK;
+ write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
+
+ /* Lock down ABASE and sleep stretching policy */
+ reg32 = read32(pmcbase + GEN_PMCON_B);
+ reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
+ write32(pmcbase + GEN_PMCON_B, reg32);
+
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ pmcbase = pmc_mmio_regs();
+ reg8 = read8(pmcbase + GEN_PMCON_B);
+ reg8 |= SMI_LOCK;
+ write8(pmcbase + GEN_PMCON_B, reg8);
+ }
+}
+
+static void dmi_lockdown_cfg(void)
+{
+ /*
+ * GCS reg of DMI
+ *
+ * When set, prevents GCS.BBS from being changed
+ * GCS.BBS: (Boot BIOS Strap) This field determines the destination
+ * of accesses to the BIOS memory range.
+ * Bits Description
+ * “0b”: SPI
+ * “1b”: LPC/eSPI
+ */
+ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
+}
+
+static void spi_lockdown_cfg(int chipset_lockdown)
+{
+ /* Set FAST_SPI opcode menu */
+ fast_spi_set_opcode_menu();
+
+ /* Discrete Lock Flash PR registers */
+ fast_spi_pr_dlock();
+
+ /* Lock FAST_SPIBAR */
+ fast_spi_lock_bar();
+
+ /* Set Bios Interface Lock, Bios Lock */
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ /* Bios Interface Lock */
+ fast_spi_set_bios_interface_lock_down();
+
+ /* Bios Lock */
+ fast_spi_set_lock_enable();
+ }
+}
+
+static void platform_lockdown_config(void *unused)
+{
+ int chipset_lockdown = 0;
+
+ chipset_lockdown = soc_get_lockdown_config();
+ if (chipset_lockdown < 0)
+ return;
+
+ /* SPI lock down configuration */
+ spi_lockdown_cfg(chipset_lockdown);
+
+ /* DMI lock down configuration */
+ dmi_lockdown_cfg();
+
+ /* PMC lock down configuration */
+ pmc_lockdown_cfg(chipset_lockdown);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
+ NULL);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3587d8fd69c6ac7d3d772401969258c3f3600809
Gerrit-Change-Number: 26026
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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