<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26026">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/basecode: Add new folder PCH for common code<br><br>Create a new folder named "pch" inside basecode directory which will<br>contain common code which relies on PCH. Currently adding support for<br>CNL PCH known as CNP.<br><br>In this patch, creating common lockdown file inside PCH. When user<br>selects "SOC_INTEL_COMMON_BASECODE_PCH_CNP" kconfig then it<br>automatically selects lockdown file from basecode instead of using it<br>from PCH. This also requires soc to implement soc specific function<br>which returns soc specific lockdown configuration.<br><br>BUG=none<br>BRANCH=none<br>TEST=code compiles with different configurations<br><br>Change-Id: I3587d8fd69c6ac7d3d772401969258c3f3600809<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>A src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h<br>A src/soc/intel/common/basecode/pch/Kconfig<br>A src/soc/intel/common/basecode/pch/Makefile.inc<br>A src/soc/intel/common/basecode/pch/lockdown.c<br>4 files changed, 151 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/26026/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h b/src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h</span><br><span>new file mode 100644</span><br><span>index 0000000..d16e23c</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/include/intelbasecode/pch/lockdown.h</span><br><span>@@ -0,0 +1,31 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef SOC_INTEL_COMMON_BASECODE_PCH_LOCKDOWN_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define SOC_INTEL_COMMON_BASECODE_PCH_LOCKDOWN_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function will get lockdown config specific to soc.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Each SOC using lockdown functionality should implement following strong</span><br><span style="color: hsl(120, 100%, 40%);">+ * function which returns proper lockdown config value.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Return values:</span><br><span style="color: hsl(120, 100%, 40%);">+ * -1 = Error = Unable to find device</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0 = CHIPSET_LOCKDOWN_FSP = use FSP's lockdown functionality to lockdown Ips</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown IPs</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int soc_get_lockdown_config(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span>diff --git a/src/soc/intel/common/basecode/pch/Kconfig b/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>new file mode 100644</span><br><span>index 0000000..b7a176b</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/pch/Kconfig</span><br><span>@@ -0,0 +1,10 @@</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BASECODE_PCH_CNP</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_PCH_CNP_LOCKDOWN</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_COMMON_BASECODE_PCH_CNP_LOCKDOWN</span><br><span style="color: hsl(120, 100%, 40%);">+ bool</span><br><span style="color: hsl(120, 100%, 40%);">+ default n</span><br><span style="color: hsl(120, 100%, 40%);">+ help</span><br><span style="color: hsl(120, 100%, 40%);">+ "Use lockdown from common block basecode instead of soc"</span><br><span>diff --git a/src/soc/intel/common/basecode/pch/Makefile.inc b/src/soc/intel/common/basecode/pch/Makefile.inc</span><br><span>new file mode 100644</span><br><span>index 0000000..e99c5b9</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/pch/Makefile.inc</span><br><span>@@ -0,0 +1 @@</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_PCH_CNP_LOCKDOWN)+= lockdown.c</span><br><span>diff --git a/src/soc/intel/common/basecode/pch/lockdown.c b/src/soc/intel/common/basecode/pch/lockdown.c</span><br><span>new file mode 100644</span><br><span>index 0000000..d60fbee</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/common/basecode/pch/lockdown.c</span><br><span>@@ -0,0 +1,109 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <bootstate.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/pch/lockdown.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelblocks/pcr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pcr_ids.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/pm.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <string.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_GCS 0x274C</span><br><span style="color: hsl(120, 100%, 40%);">+#define PCR_DMI_GCS_BILD (1 << 0)</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void pmc_lockdown_cfg(int chipset_lockdown)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t *pmcbase, reg8;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32, pmsyncreg;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMSYNC */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+ pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);</span><br><span style="color: hsl(120, 100%, 40%);">+ pmsyncreg |= PMSYNC_LOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock down ABASE and sleep stretching policy */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read32(pmcbase + GEN_PMCON_B);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);</span><br><span style="color: hsl(120, 100%, 40%);">+ write32(pmcbase + GEN_PMCON_B, reg32);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 = read8(pmcbase + GEN_PMCON_B);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg8 |= SMI_LOCK;</span><br><span style="color: hsl(120, 100%, 40%);">+ write8(pmcbase + GEN_PMCON_B, reg8);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void dmi_lockdown_cfg(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /*</span><br><span style="color: hsl(120, 100%, 40%);">+ * GCS reg of DMI</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * When set, prevents GCS.BBS from being changed</span><br><span style="color: hsl(120, 100%, 40%);">+ * GCS.BBS: (Boot BIOS Strap) This field determines the destination</span><br><span style="color: hsl(120, 100%, 40%);">+ * of accesses to the BIOS memory range.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Bits Description</span><br><span style="color: hsl(120, 100%, 40%);">+ * “0b”: SPI</span><br><span style="color: hsl(120, 100%, 40%);">+ * “1b”: LPC/eSPI</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void spi_lockdown_cfg(int chipset_lockdown)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set FAST_SPI opcode menu */</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_set_opcode_menu();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Discrete Lock Flash PR registers */</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_pr_dlock();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Lock FAST_SPIBAR */</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_lock_bar();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set Bios Interface Lock, Bios Lock */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bios Interface Lock */</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_set_bios_interface_lock_down();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Bios Lock */</span><br><span style="color: hsl(120, 100%, 40%);">+ fast_spi_set_lock_enable();</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void platform_lockdown_config(void *unused)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ int chipset_lockdown = 0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ chipset_lockdown = soc_get_lockdown_config();</span><br><span style="color: hsl(120, 100%, 40%);">+ if (chipset_lockdown < 0)</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* SPI lock down configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ spi_lockdown_cfg(chipset_lockdown);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* DMI lock down configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ dmi_lockdown_cfg();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* PMC lock down configuration */</span><br><span style="color: hsl(120, 100%, 40%);">+ pmc_lockdown_cfg(chipset_lockdown);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,</span><br><span style="color: hsl(120, 100%, 40%);">+ NULL);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26026">change 26026</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26026"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3587d8fd69c6ac7d3d772401969258c3f3600809 </div>
<div style="display:none"> Gerrit-Change-Number: 26026 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>