[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Use lockdown feature from common pool
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Thu May 3 11:30:23 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26027
Change subject: soc/intel/cannonlake: Use lockdown feature from common pool
......................................................................
soc/intel/cannonlake: Use lockdown feature from common pool
In previous patch, we have tried to push lockdown functionality to
common base instead of keeping it soc specific. In this patch, we'll use
common lockdown and remove the file from soc.
We need to implement soc specific function which returns soc specific
configuration. This function is part of chip_config.c file which will
have more chip specific configuration function for various blocks/IP.
BUG=none
BRANCH=none
TEST=Code compiles with different configurations
Change-Id: I348e80fc66259b3ed9da80ad5d7ee299a4b7c618
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/chip_config.c
M src/soc/intel/cannonlake/include/soc/pmc.h
D src/soc/intel/cannonlake/lockdown.c
5 files changed, 41 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/26027/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 541e516..bd97d0f 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -42,6 +42,8 @@
select SOC_AHCI_PORT_IMPLEMENTED_INVERT
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_BASECODE
+ select SOC_INTEL_COMMON_BASECODE_PCH_CNP
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 47f06aa..6485e50 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -34,6 +34,7 @@
ramstage-y += acpi.c
ramstage-y += chip.c
+ramstage-y += chip_config.c
ramstage-y += cpu.c
ramstage-y += finalize.c
ramstage-y += gpio.c
diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c
new file mode 100644
index 0000000..8a3227d
--- /dev/null
+++ b/src/soc/intel/cannonlake/chip_config.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include "chip.h"
+#include <intelbasecode/pch/lockdown.h>
+#include <device/device.h>
+
+/*
+ * This function will return SOC specific lockdown configuration.
+ * Function can return 3 possible values:
+ * 1. -1 = device is NULL and we need to skip lockdown
+ * 2. 0 = CHIPSET_LOCKDOWN_FSP = Use FSP to lockdown IPs
+ * 3. 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown Ips
+ */
+int soc_get_lockdown_config(void)
+{
+ const struct soc_intel_cannonlake_config *config;
+ struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
+
+ if (dev == NULL || dev->chip_info == NULL)
+ return -1;
+
+ config = dev->chip_info;
+
+ return config->chipset_lockdown;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h
index b794ede..4db2d29 100644
--- a/src/soc/intel/cannonlake/include/soc/pmc.h
+++ b/src/soc/intel/cannonlake/include/soc/pmc.h
@@ -108,7 +108,7 @@
#define DSX_CFG_MASK (0x1f << 0)
#define PMSYNC_TPR_CFG 0x18C4
-#define PCH2CPU_TPR_CFG_LOCK (1 << 31)
+#define PMSYNC_LOCK (1 << 31)
#define PCH2CPU_TT_EN (1 << 26)
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC
diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c
deleted file mode 100644
index dba5901..0000000
--- a/src/soc/intel/cannonlake/lockdown.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <bootstate.h>
-#include <chip.h>
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <string.h>
-
-#define PCR_DMI_GCS 0x274C
-#define PCR_DMI_GCS_BILD (1 << 0)
-
-static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
-{
- uint8_t *pmcbase;
- uint32_t reg32, pmsyncreg;
-
- /* PMSYNC */
- pmcbase = pmc_mmio_regs();
- pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
- pmsyncreg |= PMSYNC_LOCK;
- write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
-
- /* Lock down ABASE and sleep stretching policy */
- reg32 = read32(pmcbase + GEN_PMCON_B);
- reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
- write32(pmcbase + GEN_PMCON_B, reg32);
-
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
- pmcbase = pmc_mmio_regs();
- reg8 = read8(pmcbase + GEN_PMCON_B);
- reg8 |= SMI_LOCK;
- write8(pmcbase + GEN_PMCON_B, reg8);
- }
-}
-
-static void dmi_lockdown_cfg(void)
-{
- /*
- * GCS reg of DMI
- *
- * When set, prevents GCS.BBS from being changed
- * GCS.BBS: (Boot BIOS Strap) This field determines the destination
- * of accesses to the BIOS memory range.
- * Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
- */
- pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
-}
-
-static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config)
-{
- /* Set FAST_SPI opcode menu */
- fast_spi_set_opcode_menu();
-
- /* Discrete Lock Flash PR registers */
- fast_spi_pr_dlock();
-
- /* Lock FAST_SPIBAR */
- fast_spi_lock_bar();
-
- /* Set Bios Interface Lock, Bios Lock */
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
- /* Bios Interface Lock */
- fast_spi_set_bios_interface_lock_down();
-
- /* Bios Lock */
- fast_spi_set_lock_enable();
- }
-}
-
-static void platform_lockdown_config(void *unused)
-{
- struct soc_intel_cannonlake_config *config;
- struct device *dev;
-
- dev = PCH_DEV_SPI;
- /* Check if device is valid, else return */
- if (dev == NULL || dev->chip_info == NULL)
- return;
-
- config = dev->chip_info;
-
- /* SPI lock down configuration */
- spi_lockdown_cfg(config);
-
- /* DMI lock down configuration */
- dmi_lockdown_cfg();
-
- /* PMC lock down configuration */
- pmc_lockdown_cfg(config);
-}
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
- NULL);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I348e80fc66259b3ed9da80ad5d7ee299a4b7c618
Gerrit-Change-Number: 26027
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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