<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26027">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Use lockdown feature from common pool<br><br>In previous patch, we have tried to push lockdown functionality to<br>common base instead of keeping it soc specific. In this patch, we'll use<br>common lockdown and remove the file from soc.<br><br>We need to implement soc specific function which returns soc specific<br>configuration. This function is part of chip_config.c file which will<br>have more chip specific configuration function for various blocks/IP.<br><br>BUG=none<br>BRANCH=none<br>TEST=Code compiles with different configurations<br><br>Change-Id: I348e80fc66259b3ed9da80ad5d7ee299a4b7c618<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/chip_config.c<br>M src/soc/intel/cannonlake/include/soc/pmc.h<br>D src/soc/intel/cannonlake/lockdown.c<br>5 files changed, 41 insertions(+), 114 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/26027/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig</span><br><span>index 541e516..bd97d0f 100644</span><br><span>--- a/src/soc/intel/cannonlake/Kconfig</span><br><span>+++ b/src/soc/intel/cannonlake/Kconfig</span><br><span>@@ -42,6 +42,8 @@</span><br><span> select SOC_AHCI_PORT_IMPLEMENTED_INVERT</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_PCH_CNP</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_ACPI</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>index 47f06aa..6485e50 100644</span><br><span>--- a/src/soc/intel/cannonlake/Makefile.inc</span><br><span>+++ b/src/soc/intel/cannonlake/Makefile.inc</span><br><span>@@ -34,6 +34,7 @@</span><br><span> </span><br><span> ramstage-y += acpi.c</span><br><span> ramstage-y += chip.c</span><br><span style="color: hsl(120, 100%, 40%);">+ramstage-y += chip_config.c</span><br><span> ramstage-y += cpu.c</span><br><span> ramstage-y += finalize.c</span><br><span> ramstage-y += gpio.c</span><br><span>diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c</span><br><span>new file mode 100644</span><br><span>index 0000000..8a3227d</span><br><span>--- /dev/null</span><br><span>+++ b/src/soc/intel/cannonlake/chip_config.c</span><br><span>@@ -0,0 +1,37 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#include "chip.h"</span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/pch/lockdown.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <device/device.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function will return SOC specific lockdown configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Function can return 3 possible values:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1. -1 = device is NULL and we need to skip lockdown</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2. 0 = CHIPSET_LOCKDOWN_FSP = Use FSP to lockdown IPs</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3. 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown Ips</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int soc_get_lockdown_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev == NULL || dev->chip_info == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return config->chipset_lockdown;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>index b794ede..4db2d29 100644</span><br><span>--- a/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>+++ b/src/soc/intel/cannonlake/include/soc/pmc.h</span><br><span>@@ -108,7 +108,7 @@</span><br><span> #define DSX_CFG_MASK (0x1f << 0)</span><br><span> </span><br><span> #define PMSYNC_TPR_CFG 0x18C4</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCH2CPU_TPR_CFG_LOCK (1 << 31)</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMSYNC_LOCK (1 << 31)</span><br><span> #define PCH2CPU_TT_EN (1 << 26)</span><br><span> </span><br><span> #define PCH_PWRM_ACPI_TMR_CTL 0x18FC</span><br><span>diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c</span><br><span>deleted file mode 100644</span><br><span>index dba5901..0000000</span><br><span>--- a/src/soc/intel/cannonlake/lockdown.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,113 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <bootstate.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <chip.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pcr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pcr_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_GCS 0x274C</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_GCS_BILD (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pmc_lockdown_cfg(const struct soc_intel_cannonlake_config *config)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t *pmcbase;</span><br><span style="color: hsl(0, 100%, 40%);">- uint32_t reg32, pmsyncreg;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PMSYNC */</span><br><span style="color: hsl(0, 100%, 40%);">- pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(0, 100%, 40%);">- pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);</span><br><span style="color: hsl(0, 100%, 40%);">- pmsyncreg |= PMSYNC_LOCK;</span><br><span style="color: hsl(0, 100%, 40%);">- write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock down ABASE and sleep stretching policy */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = read32(pmcbase + GEN_PMCON_B);</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);</span><br><span style="color: hsl(0, 100%, 40%);">- write32(pmcbase + GEN_PMCON_B, reg32);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {</span><br><span style="color: hsl(0, 100%, 40%);">- pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = read8(pmcbase + GEN_PMCON_B);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= SMI_LOCK;</span><br><span style="color: hsl(0, 100%, 40%);">- write8(pmcbase + GEN_PMCON_B, reg8);</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dmi_lockdown_cfg(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * GCS reg of DMI</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * When set, prevents GCS.BBS from being changed</span><br><span style="color: hsl(0, 100%, 40%);">- * GCS.BBS: (Boot BIOS Strap) This field determines the destination</span><br><span style="color: hsl(0, 100%, 40%);">- * of accesses to the BIOS memory range.</span><br><span style="color: hsl(0, 100%, 40%);">- * Bits Description</span><br><span style="color: hsl(0, 100%, 40%);">- * “0b”: SPI</span><br><span style="color: hsl(0, 100%, 40%);">- * “1b”: LPC/eSPI</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void spi_lockdown_cfg(const struct soc_intel_cannonlake_config *config)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set FAST_SPI opcode menu */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_set_opcode_menu();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Discrete Lock Flash PR registers */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_pr_dlock();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock FAST_SPIBAR */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_lock_bar();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Bios Interface Lock, Bios Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bios Interface Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_set_bios_interface_lock_down();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bios Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_set_lock_enable();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void platform_lockdown_config(void *unused)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct soc_intel_cannonlake_config *config;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = PCH_DEV_SPI;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check if device is valid, else return */</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev == NULL || dev->chip_info == NULL)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SPI lock down configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- spi_lockdown_cfg(config);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* DMI lock down configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- dmi_lockdown_cfg();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PMC lock down configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- pmc_lockdown_cfg(config);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,</span><br><span style="color: hsl(0, 100%, 40%);">- NULL);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26027">change 26027</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I348e80fc66259b3ed9da80ad5d7ee299a4b7c618 </div>
<div style="display:none"> Gerrit-Change-Number: 26027 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>