[coreboot-gerrit] Change in coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
Julien Viard de Galbert (Code Review)
gerrit at coreboot.org
Thu Mar 29 15:08:00 CEST 2018
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25436
Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
......................................................................
mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce
Signed-off-by: Julien Viard de Galbert <jviarddegalbert at online.net>
---
A src/mainboard/scaleway/tagada/gpio_defs.h
M src/mainboard/scaleway/tagada/hsio.c
M src/mainboard/scaleway/tagada/hsio.h
3 files changed, 103 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/25436/1
diff --git a/src/mainboard/scaleway/tagada/gpio_defs.h b/src/mainboard/scaleway/tagada/gpio_defs.h
new file mode 100644
index 0000000..6c1ac1c
--- /dev/null
+++ b/src/mainboard/scaleway/tagada/gpio_defs.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 - 2018 Online SAS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MAINBOARD_GPIO_DEFS_H
+#define _MAINBOARD_GPIO_DEFS_H
+
+#include <soc/gpio_defs.h>
+
+// _GPIO_0 : LFFF: DVT_GPIO<0> : BOOTED
+#define GPIO_GPIO_0 0
+#define R_PAD_CFG_DW0_GPIO_0 0x4d8
+#define PID_GPIO_0 PID_NorthCommunity
+
+// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn
+#define GPIO_GPIO_4 4
+#define R_PAD_CFG_DW0_GPIO_4 0x568
+#define PID_GPIO_4 PID_SouthCommunity
+
+// _GPIO_5 : LFFF: M2B_CFGn : M2B_SATAn
+#define GPIO_GPIO_5 5
+#define R_PAD_CFG_DW0_GPIO_5 0x570
+#define PID_GPIO_5 PID_SouthCommunity
+
+
+// _GPIO_8 : LFFF: DVT_GPIO<1> : Baud select
+#define GPIO_GPIO_8 8
+#define R_PAD_CFG_DW0_GPIO_8 0x5c8
+#define PID_GPIO_8 PID_SouthCommunity
+
+// _GPIO_9 : LFFF: DVT_GPIO<2> : BIOS Verbose
+#define GPIO_GPIO_9 9
+#define R_PAD_CFG_DW0_GPIO_9 0x5d0
+#define PID_GPIO_9 PID_SouthCommunity
+
+#endif /* _MAINBOARD_GPIO_DEFS_H */
+
diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c
index 8e8e03e..dca80ac 100644
--- a/src/mainboard/scaleway/tagada/hsio.c
+++ b/src/mainboard/scaleway/tagada/hsio.c
@@ -14,13 +14,66 @@
* GNU General Public License for more details.
*/
+#include <arch/io.h>
+#include <console/console.h>
#include <hsio.h>
+#include <gpio_defs.h>
#include <soc/fiamux.h>
+#ifdef __RAMSTAGE__
+static void update_hsio_info_for_m2_slots(size_t num_of_entry,
+ BL_HSIO_INFORMATION *config)
+{
+ uint32_t reg32;
+ bool m2a_pcie, m2b_pcie;
+ uint8_t entry;
+
+ /* Detects modules type */
+ // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe
+ reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_4,
+ R_PAD_CFG_DW0_GPIO_4));
+ m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE)?1:0;
+ // _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe
+ reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_5,
+ R_PAD_CFG_DW0_GPIO_5));
+ m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE)?1:0;
+
+ printk(BIOS_DEBUG, "GPIO values from M2 slots A:%d B:%d "
+ "(0=SATA, 1=PCIe or not populated)\n",
+ m2a_pcie, m2b_pcie);
+
+ // HSIO default config is for PCIe, only update for SATA
+ // (also secondary PCIe lines are already set depending on SKU)
+ for (entry = 0; entry < num_of_entry; entry++) {
+ BL_ME_FIA_MUX_CONFIG *mux_config =
+ &(config[entry].FiaConfig.MuxConfiguration);
+ BL_ME_FIA_SATA_CONFIG *sata_config =
+ &(config[entry].FiaConfig.SataLaneConfiguration);
+ if (!m2a_pcie) {
+ // change Lane 14 config
+ mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel =
+ BL_ME_FIA_MUX_LANE_SATA;
+ sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel =
+ BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
+ }
+ if (!m2b_pcie) {
+ // change Lane 12 config
+ mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel =
+ BL_ME_FIA_MUX_LANE_SATA;
+ sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel =
+ BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;
+ }
+ }
+}
+#endif
+
size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
{
size_t num;
num = ARRAY_SIZE(tagada_hsio_config);
+#ifdef __RAMSTAGE__
+ update_hsio_info_for_m2_slots(num, tagada_hsio_config);
+#endif
(*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;
return num;
}
diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h
index e49fefd..6289dae 100644
--- a/src/mainboard/scaleway/tagada/hsio.h
+++ b/src/mainboard/scaleway/tagada/hsio.h
@@ -21,7 +21,7 @@
#include <fsp/util.h>
#ifndef __ACPI__
-const BL_HSIO_INFORMATION tagada_hsio_config[] = {
+DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[] = {
/*
* Supported Lanes:
* 20
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce
Gerrit-Change-Number: 25436
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert at online.net>
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