<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25436">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes<br><br>Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>A src/mainboard/scaleway/tagada/gpio_defs.h<br>M src/mainboard/scaleway/tagada/hsio.c<br>M src/mainboard/scaleway/tagada/hsio.h<br>3 files changed, 103 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/25436/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/scaleway/tagada/gpio_defs.h b/src/mainboard/scaleway/tagada/gpio_defs.h</span><br><span>new file mode 100644</span><br><span>index 0000000..6c1ac1c</span><br><span>--- /dev/null</span><br><span>+++ b/src/mainboard/scaleway/tagada/gpio_defs.h</span><br><span>@@ -0,0 +1,49 @@</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This file is part of the coreboot project.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2017 - 2018 Online SAS</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(120, 100%, 40%);">+ * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(120, 100%, 40%);">+ * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(120, 100%, 40%);">+ * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(120, 100%, 40%);">+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(120, 100%, 40%);">+ * GNU General Public License for more details.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef _MAINBOARD_GPIO_DEFS_H</span><br><span style="color: hsl(120, 100%, 40%);">+#define _MAINBOARD_GPIO_DEFS_H</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <soc/gpio_defs.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// _GPIO_0 : LFFF: DVT_GPIO<0> : BOOTED</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPIO_0 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_PAD_CFG_DW0_GPIO_0 0x4d8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIO_0 PID_NorthCommunity</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPIO_4 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_PAD_CFG_DW0_GPIO_4 0x568</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIO_4 PID_SouthCommunity</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// _GPIO_5 : LFFF: M2B_CFGn : M2B_SATAn</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPIO_5 5</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_PAD_CFG_DW0_GPIO_5 0x570</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIO_5 PID_SouthCommunity</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// _GPIO_8 : LFFF: DVT_GPIO<1> : Baud select</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPIO_8 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_PAD_CFG_DW0_GPIO_8 0x5c8</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIO_8 PID_SouthCommunity</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// _GPIO_9 : LFFF: DVT_GPIO<2> : BIOS Verbose</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_GPIO_9 9</span><br><span style="color: hsl(120, 100%, 40%);">+#define R_PAD_CFG_DW0_GPIO_9 0x5d0</span><br><span style="color: hsl(120, 100%, 40%);">+#define PID_GPIO_9 PID_SouthCommunity</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#endif /* _MAINBOARD_GPIO_DEFS_H */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>diff --git a/src/mainboard/scaleway/tagada/hsio.c b/src/mainboard/scaleway/tagada/hsio.c</span><br><span>index 8e8e03e..dca80ac 100644</span><br><span>--- a/src/mainboard/scaleway/tagada/hsio.c</span><br><span>+++ b/src/mainboard/scaleway/tagada/hsio.c</span><br><span>@@ -14,13 +14,66 @@</span><br><span> * GNU General Public License for more details.</span><br><span> */</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#include <arch/io.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <console/console.h></span><br><span> #include <hsio.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <gpio_defs.h></span><br><span> #include <soc/fiamux.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __RAMSTAGE__</span><br><span style="color: hsl(120, 100%, 40%);">+static void update_hsio_info_for_m2_slots(size_t num_of_entry,</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_HSIO_INFORMATION *config)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t reg32;</span><br><span style="color: hsl(120, 100%, 40%);">+ bool m2a_pcie, m2b_pcie;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t entry;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Detects modules type */</span><br><span style="color: hsl(120, 100%, 40%);">+ // _GPIO_4 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_4,</span><br><span style="color: hsl(120, 100%, 40%);">+ R_PAD_CFG_DW0_GPIO_4));</span><br><span style="color: hsl(120, 100%, 40%);">+ m2a_pcie = (reg32 & B_PCH_GPIO_RX_STATE)?1:0;</span><br><span style="color: hsl(120, 100%, 40%);">+ // _GPIO_5 : LFFF: M2A_CFGn : M2A_SATAn : 0 SATA, 1 PCIe</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIO_5,</span><br><span style="color: hsl(120, 100%, 40%);">+ R_PAD_CFG_DW0_GPIO_5));</span><br><span style="color: hsl(120, 100%, 40%);">+ m2b_pcie = (reg32 & B_PCH_GPIO_RX_STATE)?1:0;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "GPIO values from M2 slots A:%d B:%d "</span><br><span style="color: hsl(120, 100%, 40%);">+ "(0=SATA, 1=PCIe or not populated)\n",</span><br><span style="color: hsl(120, 100%, 40%);">+ m2a_pcie, m2b_pcie);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ // HSIO default config is for PCIe, only update for SATA</span><br><span style="color: hsl(120, 100%, 40%);">+ // (also secondary PCIe lines are already set depending on SKU)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (entry = 0; entry < num_of_entry; entry++) {</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_MUX_CONFIG *mux_config =</span><br><span style="color: hsl(120, 100%, 40%);">+ &(config[entry].FiaConfig.MuxConfiguration);</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_SATA_CONFIG *sata_config =</span><br><span style="color: hsl(120, 100%, 40%);">+ &(config[entry].FiaConfig.SataLaneConfiguration);</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!m2a_pcie) {</span><br><span style="color: hsl(120, 100%, 40%);">+ // change Lane 14 config</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_config->BL_MeFiaMuxLaneMuxSel.Lane14MuxSel =</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_MUX_LANE_SATA;</span><br><span style="color: hsl(120, 100%, 40%);">+ sata_config->BL_MeFiaSataLaneSataSel.Lane14SataSel =</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!m2b_pcie) {</span><br><span style="color: hsl(120, 100%, 40%);">+ // change Lane 12 config</span><br><span style="color: hsl(120, 100%, 40%);">+ mux_config->BL_MeFiaMuxLaneMuxSel.Lane12MuxSel =</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_MUX_LANE_SATA;</span><br><span style="color: hsl(120, 100%, 40%);">+ sata_config->BL_MeFiaSataLaneSataSel.Lane12SataSel =</span><br><span style="color: hsl(120, 100%, 40%);">+ BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)</span><br><span> {</span><br><span> size_t num;</span><br><span> num = ARRAY_SIZE(tagada_hsio_config);</span><br><span style="color: hsl(120, 100%, 40%);">+#ifdef __RAMSTAGE__</span><br><span style="color: hsl(120, 100%, 40%);">+ update_hsio_info_for_m2_slots(num, tagada_hsio_config);</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span> (*p_hsio_config) = (BL_HSIO_INFORMATION *)tagada_hsio_config;</span><br><span> return num;</span><br><span> }</span><br><span>diff --git a/src/mainboard/scaleway/tagada/hsio.h b/src/mainboard/scaleway/tagada/hsio.h</span><br><span>index e49fefd..6289dae 100644</span><br><span>--- a/src/mainboard/scaleway/tagada/hsio.h</span><br><span>+++ b/src/mainboard/scaleway/tagada/hsio.h</span><br><span>@@ -21,7 +21,7 @@</span><br><span> #include <fsp/util.h></span><br><span> </span><br><span> #ifndef __ACPI__</span><br><span style="color: hsl(0, 100%, 40%);">-const BL_HSIO_INFORMATION tagada_hsio_config[] = {</span><br><span style="color: hsl(120, 100%, 40%);">+DEVTREE_CONST BL_HSIO_INFORMATION tagada_hsio_config[] = {</span><br><span> /*</span><br><span> * Supported Lanes:</span><br><span> * 20</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25436">change 25436</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce </div>
<div style="display:none"> Gerrit-Change-Number: 25436 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>