[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Configure MCA
Julien Viard de Galbert (Code Review)
gerrit at coreboot.org
Thu Mar 29 15:07:59 CEST 2018
Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25433
Change subject: soc/intel/denverton_ns: Configure MCA
......................................................................
soc/intel/denverton_ns: Configure MCA
Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba
Signed-off-by: Julien Viard de Galbert <jviarddegalbert at online.net>
---
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/include/soc/msr.h
2 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/25433/1
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index 12fda1c..6c1298e 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -35,12 +35,41 @@
static struct smm_relocation_attrs relo_attrs;
+static void dnv_configure_mca(void)
+{
+ msr_t msr;
+ int num_banks;
+ struct cpuid_result cpuid_regs;
+
+ /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE
+ * and CPUID.(EAX=1):EDX[14]==1 MCA*/
+ cpuid_regs = cpuid(1);
+ if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14))
+ return;
+
+ msr = rdmsr(IA32_MCG_CAP);
+ num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK;
+ if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) {
+ /* Enable all error logging */
+ msr.lo = msr.hi = 0xffffffff;
+ wrmsr(IA32_MCG_CTL, msr);
+ }
+
+ /* TODO(adurbin): This should only be done on a cold boot. Also, some
+ of these banks are core vs package scope. For now every CPU clears
+ every bank. */
+ mca_configure();
+}
+
static void denverton_core_init(device_t cpu)
{
msr_t msr;
printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n");
+ /* Clear out pending MCEs */
+ dnv_configure_mca();
+
/* Enable Fast Strings */
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= FAST_STRINGS_ENABLE_BIT;
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
index d56cc65..05ccc65 100644
--- a/src/soc/intel/denverton_ns/include/soc/msr.h
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -29,6 +29,11 @@
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_FEATURE_CONFIG 0x13c
+#define IA32_MCG_CAP 0x179
+#define IA32_MCG_CAP_COUNT_MASK 0xff
+#define IA32_MCG_CAP_CTL_P_BIT 8
+#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT)
+#define IA32_MCG_CTL 0x17b
#define SMM_MCA_CAP_MSR 0x17d
#define SMM_CPU_SVRSTR_BIT 57
#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba
Gerrit-Change-Number: 25433
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert at online.net>
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