<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25433">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton_ns: Configure MCA<br><br>Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/soc/intel/denverton_ns/cpu.c<br>M src/soc/intel/denverton_ns/include/soc/msr.h<br>2 files changed, 34 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/25433/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c</span><br><span>index 12fda1c..6c1298e 100644</span><br><span>--- a/src/soc/intel/denverton_ns/cpu.c</span><br><span>+++ b/src/soc/intel/denverton_ns/cpu.c</span><br><span>@@ -35,12 +35,41 @@</span><br><span> </span><br><span> static struct smm_relocation_attrs relo_attrs;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void dnv_configure_mca(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ msr_t msr;</span><br><span style="color: hsl(120, 100%, 40%);">+ int num_banks;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuid_result cpuid_regs;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE</span><br><span style="color: hsl(120, 100%, 40%);">+ * and CPUID.(EAX=1):EDX[14]==1 MCA*/</span><br><span style="color: hsl(120, 100%, 40%);">+ cpuid_regs = cpuid(1);</span><br><span style="color: hsl(120, 100%, 40%);">+ if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14))</span><br><span style="color: hsl(120, 100%, 40%);">+ return;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ msr = rdmsr(IA32_MCG_CAP);</span><br><span style="color: hsl(120, 100%, 40%);">+ num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+ if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable all error logging */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo = msr.hi = 0xffffffff;</span><br><span style="color: hsl(120, 100%, 40%);">+ wrmsr(IA32_MCG_CTL, msr);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* TODO(adurbin): This should only be done on a cold boot. Also, some</span><br><span style="color: hsl(120, 100%, 40%);">+ of these banks are core vs package scope. For now every CPU clears</span><br><span style="color: hsl(120, 100%, 40%);">+ every bank. */</span><br><span style="color: hsl(120, 100%, 40%);">+ mca_configure();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void denverton_core_init(device_t cpu)</span><br><span> {</span><br><span> msr_t msr;</span><br><span> </span><br><span> printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n");</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* Clear out pending MCEs */</span><br><span style="color: hsl(120, 100%, 40%);">+ dnv_configure_mca();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /* Enable Fast Strings */</span><br><span> msr = rdmsr(IA32_MISC_ENABLE);</span><br><span> msr.lo |= FAST_STRINGS_ENABLE_BIT;</span><br><span>diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>index d56cc65..05ccc65 100644</span><br><span>--- a/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>+++ b/src/soc/intel/denverton_ns/include/soc/msr.h</span><br><span>@@ -29,6 +29,11 @@</span><br><span> #define MSR_PMG_CST_CONFIG_CONTROL 0xe2</span><br><span> #define MSR_PMG_IO_CAPTURE_BASE 0xe4</span><br><span> #define MSR_FEATURE_CONFIG 0x13c</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CAP 0x179</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CAP_COUNT_MASK 0xff</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CAP_CTL_P_BIT 8</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define IA32_MCG_CTL 0x17b</span><br><span> #define SMM_MCA_CAP_MSR 0x17d</span><br><span> #define SMM_CPU_SVRSTR_BIT 57</span><br><span> #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25433">change 25433</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba </div>
<div style="display:none"> Gerrit-Change-Number: 25433 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>